參數(shù)資料
型號: M34551M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù): 59/71頁
文件大?。?/td> 966K
代理商: M34551M4-XXXFP
59
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CONTROL REGISTERS (CONTINUED)
I13
I12
I11
I10
Not used
Interrupt valid waveform for INT pin
selection bit (Note 2)
Not used
0
1
0
1
0
1
0
1
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)
This bit has no function, but read/write is enabled.
Interrupt control register I1
R/W
at reset : 00002
at power down : state retained
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
0
1
0
1
0
1
0
1
at reset : 00002
at power down : state retained
Pull-up control register PU0
R/W
PU03
PU02
PU01
PU00
System clock (STCK) selection bit
f(XCIN) oscillation circuit control bit
f(XIN) oscillation circuit control bit
Clock selection bit
at reset : 10002
at power down : state retained
Clock control register MR
R/W
MR3
MR2
MR1
MR0
MR0=0 f(XIN)
MR0=1 f(XCIN)
MR0=0 f(XIN)/4
MR0=1 f(XCIN)/4
f(XCIN) oscillation stop, ports D6 and D7 selected
f(XCIN) oscillation enabled, ports D6 and D7 not selected
Oscillation enabled
Oscillation stop
f(XIN)
f(XCIN)
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of
I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
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