參數(shù)資料
型號(hào)： M34551M4
廠(chǎng)商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 單芯片4位CMOS微機(jī)紅外遙控器
文件頁(yè)數(shù)： 22/68頁(yè)
文件大小： 698K
代理商： M34551M4
22
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program runs wild. Watchdog timer consists of timer 2, watchdog
timer enable flag (WEF), and watchdog timer flag (WDF).
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1.” At this time, the watchdog
timer starts operating. When the WEF flag is set to “1,” it cannot
be cleared to “0” until system reset is performed. Also, when the
WRST instruction is not executed once, watchdog timer does
not operate because the WEF flag retains “0.”
When the watchdog timer is operating, the WDF flag is set to “1”
every time the bit 12 of timer 2 is cleared from “1” to “0.” This
means that count is performed 8192 times. When the bit 12 of
timer 2 is cleared from “1” to “0” while the WDF flag is set to “1,”
the internal reset signal is generated and system reset is
performed.
The WDF flag can be cleared to “0” with the WRST instruction.
In the RAM back-up mode, through timer 2 count operation stops,
its count value is retained and the WDF flag is initialized.
In the clock operating mode, timer 2 count operation is continued
and the WDF flag is initialized.
When using the watchdog timer, execute the WRST instruction
at a certain cycle which consists of timer 2’s 8191 counts or less
to keep the microcomputer operation normal.
Fig. 20 Watchdog timer function
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
The contents of the WDF flag are initialized in the RAM back-up
mode.
If the WDF flag is set to “1” at the same time that the
microcomputer enters the RAM back-up mode, system reset may
be performed.
When using the watchdog timer and the RAM back-up mode,
initialize the WDF flag with the WRST instruction just before the
microcomputer enters the RAM back-up mode (refer to Figure
21).
WRST ; Clear WDF flag
POF2
EPOF ; POF instruction execution enabled
(RAM back-up mode)
Oscillation stop
1FFF
16
0000
16
Value of timer 2
Internal reset
signal
WRST instruction
execution
System reset
WRST instruction
execution
WEF flag
3FFF
16
WDF flag
“1”
“0”
“1”
“0”
“H”
“L”
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