參數(shù)資料
型號(hào)： M34551M4
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 單芯片4位CMOS微機(jī)紅外遙控器
文件頁(yè)數(shù)： 46/68頁(yè)
文件大小： 698K
代理商： M34551M4
Skip condition
Detailed description
C
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
(Y) = 15
(Y) = 0
–
Continuous
description
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–
–
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After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR
2
DR
1
DR
0
A
3
A
2
A
1
A
0
)
2
specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
46
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