參數(shù)資料
型號(hào)： M34556M8H-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 76/147頁
文件大?。?/td> 1087K
代理商： M34556M8H-XXXFP
Rev.3.02
Dec 22, 2006
page 32 of 142
REJ03B0025-0302
4556 Group
Table 10 Timer related registers
CNTR pin output invalid
CNTR pin output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK)/2 signal output
CNTR pin output control bit
PWM signal interrupt valid waveform/
return level selection bit
Timer 2 control bit
Timer 2 count soruce selection bit
0
1
0
1
0
1
0
1
Timer control register W2
at power down : 00002
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: Port C output is invalid when CNTR input is selected for the timer 1 count source.
W23
W22
W21
W20
W11
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 3 underflow signal (T3UDF)
CNTR input
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 1 control bit
Timer 1 count source selection bits
(Note 3)
0
1
0
1
W10
0
1
0
1
Timer control register W1
R/W
TAW1/TW1A
at power down : state retained
at reset : 00002
W13
W12
W11
W10
W31
0
1
XCIN input
Prescaler output (ORCLK)
Stop (Initial state)
Operating
Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
Timer 3 count auto-stop circuit selection
bit
Timer 3 control bit
Timer 3 count value selection bits
0
1
0
1
W30
0
1
0
1
Timer control register W3
at power down : state retained
at reset : 00002
W33
W32
W31
W30
R/W
TAW2/TW2A
R/W
TAW3/TW3A
0
1
Stop (state retained)
Operating
Prescaler control bit
Timer control register PA
W
TPAA
at power down : 02
at reset : 02
PA0
Stop (state retained)
Operating
Bit 4 (T34) of timer 3
System clock (STCK)
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
Rising edge
Timer LC control bit
Timer LC count source selection bit
CNTR output auto-control circuit
selection bit
CNTR pin input count edge selection bit
0
1
0
1
0
1
0
1
Timer control register W4
at power down : state retained
at reset : 00002
W43
W42
W41
W40
R/W
TAW4/TW4A
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