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參數(shù)資料
| 型號： | M34C02-W-WMB1TG |
| 廠商： | 意法半導體 |
| 英文描述： | 2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect |
| 中文描述： | 2千位串行IC總線的EEPROM內存串行存在檢測 |
| 文件頁數(shù)： | 11/31頁 |
| 文件大小： | 162K |
| 代理商： | M34C02-W-WMB1TG |
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M34C02-W, M34C02-L, M34C02-R
Device operation
11/31
3
Device operation
The device supports the I
2
C protocol. This is summarized in
Figure 5
. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The memory device is always a slave in all
communication.
3.1
Start Condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop Condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Stand-by mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
th
clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change
only
when Serial Clock
(SCL) is driven Low.
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相關代理商/技術參數(shù) |
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|---|---|
| M34C02-W-WMB6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect |
| M34C106K125AZSS | 功能描述:鉭質電容器-濕式 10uF 125volts 10% C Case RoHS:否 制造商:Vishay/Tansitor 電容:2800 uF 電壓額定值:35 V ESR:0.35 Ohms 容差:20 % 端接類型:Axial 工作溫度范圍:- 55 C to + 85 C 制造商庫存號:T4 Case 外殼直徑:9.52 mm 外殼長度:26.97 mm 外殼寬度: 外殼高度: 系列:STE 產(chǎn)品:Tantalum Wet Hermetically Sealed 封裝:Bulk |
| M34C106K125BZSS | 功能描述:鉭質電容器-濕式 10uF 125volts 10% C Case RoHS:否 制造商:Vishay/Tansitor 電容:2800 uF 電壓額定值:35 V ESR:0.35 Ohms 容差:20 % 端接類型:Axial 工作溫度范圍:- 55 C to + 85 C 制造商庫存號:T4 Case 外殼直徑:9.52 mm 外殼長度:26.97 mm 外殼寬度: 外殼高度: 系列:STE 產(chǎn)品:Tantalum Wet Hermetically Sealed 封裝:Bulk |
| M34C106M125AZSS | 制造商:Vishay Sprague 功能描述:- Bulk |
| M34C106M125BZSS | 制造商:Vishay Sprague 功能描述:- Bulk |
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