參數(shù)資料
型號(hào)： M34C02-W-WMB1TG
廠商： 意法半導(dǎo)體
英文描述： 2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
中文描述： 2千位串行IC總線的EEPROM內(nèi)存串行存在檢測(cè)
文件頁(yè)數(shù)： 6/31頁(yè)
文件大小： 162K
代理商： M34C02-W-WMB1TG
Summary description
M34C02-W, M34C02-L, M34C02-R
6/31
1
Summary description
The M34C02-W, M34C02-L and M34C02-R are 2Kbit serial EEPROM memory able to lock
permanently the data in its first half (from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial
Presence Detect. All the information concerning the DRAM module configuration (such as
its access speed, its size, its organization) can be kept write protected in the first half of the
memory.
This bottom half of the memory area can be write-protected using a specially designed
software write protection mechanism. By sending the device a specific sequence, the first
128 Bytes of the memory become permanently write protected. Care must be taken when
using this sequence as its effect cannot be reversed. In addition, the device allows the entire
memory area to be write protected, using the WC input (for example by tieing this input to
V
CC
).
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 256x8 bits.
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. ECOPACK packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com
.
I
2
C uses a two wire serial interface, comprising a bi-directional data line and a clock line.
The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I
2
C bus definition to access the memory area and a second Device Type Identifier Code
(0110) to access the Protection Register. These codes are used together with three chip
enable inputs (E2, E1, E0) so that up to eight 2Kbit devices may be attached to the I2C bus
and selected individually.
The device behaves as a slave device in the I
2
C protocol, with all memory operations
synchronized by the serial clock. Read and Write operations are initiated by a START
condition, generated by the bus master. The START condition is followed by a Device Select
Code and RW bit (as described in
Table 2
), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9
th
bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34C02-W-WMB6TG 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
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