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參數(shù)資料
| 型號： | M34E02-FDW1T |
| 廠商： | 意法半導體 |
| 英文描述： | 2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs |
| 中文描述： | 2千位串行總線的EEPROM芯片串行存在檢測的DDR2內存 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大小： | 144K |
| 代理商： | M34E02-FDW1T |
M34E02
4/23
SUMMARY DESCRIPTION
The M34E02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using two different software write
protection mechanisms. By sending the device a
specific sequence, the first 128 bytes of the
memory become write protected: permanently or
resetable. In addition, the device allows the entire
memory area to be write protected, using the WC
input (for example by tieing this input to V
CC
).
These
I
2
C-compatible
programmable memory (EEPROM) devices are
organized as 256x8 bits.
electrically
erasable
Figure 2. Logic Diagram
I
2
C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The device
carries a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition to
access the memory area and a second Device
Type Identifier Code (0110) to define the
protection. These codes are used together with
the voltage level applied on the three chip enable
inputs (E2, E1, E0).
The device behaves as a slave device in the I
2
C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 2), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Figure 3. TSSOP and MLP Connections (Top
View)
Note: 1. See the pages after page 19 for package dimensions,
and how to identify pin-1.
Table 1. Signal Names
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during power up, a Power On
Reset (POR) circuit is included. At Power-on, the
internal reset is held active until V
CC
has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any
command. In the same way, when V
CC
drops from
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command.
A stable and valid V
CC
(as defined in Table 8) must
be applied before applying any logic signal.
AI09020
3
E0-E2
SDA
VCC
M34E02
WC
SCL
VSS
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDA
VSS
SCL
WC
E1
E2
E0
VCC
AI09021
M34E02
1
2
3
4
8
7
6
5
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34E02-FDW1TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs |
| M34E02-FDW1TP | 功能描述:電可擦除可編程只讀存儲器 2Kbit Serial EE RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M34E02-FDW6G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules |
| M34E02-FDW6P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules |
| M34E02-FDW6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules |
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