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參數(shù)資料
| 型號： | M34E02-FDW1T |
| 廠商： | 意法半導體 |
| 英文描述： | 2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs |
| 中文描述： | 2千位串行總線的EEPROM芯片串行存在檢測的DDR2內存 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 144K |
| 代理商： | M34E02-FDW1T |
5/23
M34E02
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to V
CC
. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. In the
end application, E0, E1 and E2 must be directly
(not through a pull-up or pull-down resistor) con-
nected to V
CC
or V
SS
to establish the Device Se-
lect Code. When these inputs are not connected,
an internal pull-down circuitry makes (E0,E1,E2) =
(0,0,0).
The E0 input is used to detect the V
HV
voltage,
when decoding an SWP or CWP instruction.
Write Control (WC)
This input signal is provided for protecting the con-
tents of the whole memory from inadvertent write
operations. Write Control (WC) is used to enable
(when driven Low) or disable (when driven High)
write instructions to the entire memory area or to
the Protection Register.
When Write Control (WC) is tied Low or left
unconnected, the write protection of the first half of
the memory is determined by the status of the
Protection Register.
Figure 4. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
M
)
10
1000
fc = 400kHz
fc = 100kHz
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34E02-FDW1TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs |
| M34E02-FDW1TP | 功能描述:電可擦除可編程只讀存儲器 2Kbit Serial EE RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M34E02-FDW6G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules |
| M34E02-FDW6P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules |
| M34E02-FDW6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules |
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