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參數(shù)資料
| 型號： | M34S32WMN1T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page |
| 中文描述： | 32K的串行I2C總線的EEPROM與用戶定義的只讀塊和32字節(jié)檢察官頁 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 156K |
| 代理商： | M34S32WMN1T |
8/18
M34S32
Byte Write.
In the Byte Write mode the master
sends one data byte, which is acknowledged by
the memory. The master then terminates the
transfer by generating a STOP condition.
Page Write.
The Page Write mode allows up to 32
bytes to be written in a single write cycle, provided
that they are all located in the same row of 32
bytes in the memory, that is the same Address bits
(b12 to b5). The master sends one up to 32 bytes
of data, which are each acknowledged by the
memory. After each byte is transferred, the inter-
nal byte address counter (5 Least Significant Bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition. Care
must be taken to avoid address counter “roll-over”
which could result in data being overwritten.
Figure 8. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
Note that for any write mode, the generation by the
master of the STOP condition starts the internal
memory program cycle. This STOP condition will
trigger an internal memory program cycle only if
the STOP condition is internally decoded right af-
ter the ACK bit; any STOP condition decoded out
of this “10th bit” time slot will not trigger the internal
programming cycle. All inputs are disabled until
the completion of this cycle and the Memory will
not respond to any request.
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| M34S32WMN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page |
| M34S32WMN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page |
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