參數(shù)資料
型號： M368L3324BUM-LCC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
中文描述： DDR SDRAM的緩沖模塊184pin緩沖模塊基于512Mb乙芯片與64/72-bit非ECC / ECC的66 TSOP-II
文件頁數(shù)： 7/25頁
文件大?。?/td> 464K
代理商： M368L3324BUM-LCC
DDR SDRAM
256MB, 512MB, 1GB Unbuffered DIMM
Rev. 1.1 June 2005
Output Load Circuit (SSTL_2)
Output
Z0=50
CLOAD=30pF
VREF
=0.5*VDDQ
RT=50
Vtt=0.5*VDDQ
(VDD=2.5V, VDDQ=2.5V, TA= 25
°C, f=1MHz)
Parameter
Symbol
M368L3324BT(U) M368L6523BT(U) M381L6523BT(U)
Unit
Min
Max
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
41
4549575160
pF
Input capacitance(CKE0)
CIN2
34
38
42
50
44
53
pF
Input capacitance( CS0)
CIN3
34
38
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
25
30
25
30
25
30
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
6767
67
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
6767
67
pF
Data input/output capacitance (CB0~CB7)
Cout2
----
6
7
pF
Parameter
Symbol
M368L2923BT(U)
M381L2923BT(U)
Unit
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
65
816987
pF
Input capacitance(CKE0,CKE1)
CIN2
42
50
44
53
pF
Input capacitance( CS0, CS1)
CIN3
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
28
34
28
34
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
10
12
10
12
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
10
12
10
12
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
10
12
pF
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
11.0 Input/Output Capacitance
10.0 AC Operating Conditions
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M368L3324CUS-CLCC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module
M368L3324DUS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M368L3324DUS-CB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M368L3324DUS-CCC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M368L3324DUS-LB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
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