參數(shù)資料
型號: M368L5623MTN
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR SDRAM Unbuffered Module
中文描述: DDR SDRAM的緩沖模塊
文件頁數(shù): 17/17頁
文件大?。?/td> 250K
代理商: M368L5623MTN
Preliminary
2GB Unbuffered DIMM
Rev. 0.0 April 2004
DDR SDRAM
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specifications are related to a Vref envelope that has been bandwidth limited 20MHz.
Output Load Circuit (SSTL_2)
Output
Z0=50
CLOAD=30pF
VREF
=0.5*VDDQ
RT=50
Vtt=0.5*VDDQ
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25
°C, f=1MHz)
Parameter
Symbol
M368L5623MTN
M381L5623MTM
Unit
Min
Max
Min
Max
Input capacitance(A0 ~ A13, BA0 ~ BA1,RAS,CAS,WE )
CIN1
65816987
pF
Input capacitance(CKE0,CKE1)
CIN2
42
50
44
53
pF
Input capacitance( CS0, CS1)
CIN3
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
28
34
28
34
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
10
12
10
12
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
10
12
10
12
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
10
12
pF
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
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