參數(shù)資料
型號： M368L6523BUM-LCC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
中文描述： DDR SDRAM的緩沖模塊184pin緩沖模塊基于512Mb乙芯片與64/72-bit非ECC / ECC的66 TSOP-II
文件頁數(shù)： 13/25頁
文件大?。?/td> 464K
代理商： M368L6523BUM-LCC
DDR SDRAM
256MB, 512MB, 1GB Unbuffered DIMM
Rev. 1.1 June 2005
(V=Valid, X=Don
′t Care, H=Logic High, L=Logic Low)
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
A0 ~ A9
A11, A12
Note
Register
Extended MRS
H
X
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
OP CODE
1, 2
Refresh
Auto Refresh
H
LL
L
H
X
3
Self
Refresh
Entry
L
3
Exit
L
H
LH
HH
X
3
HX
X
3
Bank Active & Row Addr.
H
X
L
H
V
Row Address
(A0~A9, A11,A12)
Read &
Column Address
Auto Precharge Disable
HX
L
H
L
H
V
L
Column
Address
4
Auto Precharge Enable
H
4
Write &
Column Address
Auto Precharge Disable
HX
L
H
L
V
L
Column
Address
4
Auto Precharge Enable
H
4, 6
Burst Stop
H
X
L
H
L
X
7
Precharge
Bank Selection
HX
L
H
L
VL
X
All Banks
X
H
5
Active Power Down
Entry
H
L
HX
X
LV
V
Exit
L
H
X
Precharge Power Down Mode
Entry
H
L
HX
X
LH
HH
Exit
L
H
HX
X
LV
V
DM
H
X
8
No operation (NOP) : Not defined
H
X
HX
X
9
LH
HH
9
16.0 Command Truth Table
相關PDF資料
PDF描述
M368L6523BUN-LB3 DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
M36L0T7050T0ZAQE 128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package
M36L0T7050T0ZAQF 128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package
M36L0T7050T0ZAQT 128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package
M36L0T7050B0 128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package
相關代理商/技術參數(shù)
參數(shù)描述
M368L6523BUN-CB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
M368L6523BUN-LB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
M368L6523CUS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module
M368L6523CUS-CCC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module
M368L6523DUS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Product Guide
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