- 您現(xiàn)在的位置：買賣IC網 > PDF目錄359056 > M36DR432BD12ZA6T (意法半導體) 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product PDF資料下載
參數(shù)資料
| 型號： | M36DR432BD12ZA6T |
| 廠商： | 意法半導體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，頁閃存和4兆位的256Kb x16的SRAM，多個存儲產品 |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 834K |
| 代理商： | M36DR432BD12ZA6T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
M36DR432AD, M36DR432BD
24/52
SRAM COMPONENT
The SRAM is a 4 Mbit (256Kb x16) low-power con-
sumption memory array with low V
DDS
data reten-
tion.
SRAM Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 2).
Read.
Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at V
IH
with
Output Enable (GS) at V
IL
, Chip Enable ES and
UBS, LBS combinations are asserted.
Valid data will be available at the output pins within
t
AVQV
after the last stable address, provided that
GS is Low and ES is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t
ELQV
or
t
GLQV
) rather than the address. Data out may be
indeterminate at t
ELQX
and t
GLQX
, but data lines
will always be valid at t
AVQV
(see Table 23, Figures
17 and 18).
Write.
Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and ES pins are at V
IL
. Either the Chip En-
able input (ES) or the Write Enable input (WS)
must be de-asserted during address transitions for
subsequent write cycles. Write begins with the
concurrence of Chip Enable being active and WS
at V
IL
. A Write begins at the latest transition
among ES going to V
IL
and WS going to V
IL
.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as t
AVWL
and t
AVEL
respectively, and is determined by the latter occur-
ring edge. The Write cycle can be terminated by
the rising edge of ES or the rising edge of WS,
whichever occurs first.
If the Output is enabled (ES=V
IL
and GS=V
IL
),
then WS will return the outputs to high impedance
within t
WLQZ
of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for t
DVWH
before the ris-
ing edge of Write Enable, or for t
DVEH
before the
rising edge of ES, whichever occurs first, and re-
main valid for t
WHDX
and t
EHAX
(see Table 24, Fig-
ure 20, 22, 24).
Standby/Power-Down.
The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 23, Figure
19) whenever either Chip Enable is de-asserted
(ES=V
IH
).
Data Retention.
The SRAM data retention per-
formances as V
DDS
go down to V
DR
are described
in Table 25 and Figure 24. In ES controlled data
retention mode, minimum standby current mode is
entered when ES
≥
V
DDS
– 0.2V.
Output Disable.
The data outputs are high im-
pedance when the Output Enable (GS) is at V
IH
with Write Enable (WS) at V
IH
.
相關PDF資料 |
PDF描述 |
|---|---|
| M36DR432DZA | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432-ZAT | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432A100ZA6T | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432A120ZA6T | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432AD | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M36DR432BD85ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
| M36DR432BDZA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
| M36DR432BZA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432C | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| M36DR432CA10ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
發(fā)布緊急采購，3分鐘左右您將得到回復。