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參數(shù)資料
| 型號： | M36LLR876B0 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| 中文描述： | 256 128兆位（多銀行，多層次，突發(fā)）64兆位閃存（突發(fā)）移動存儲芯片，1.8V電源，多芯片封裝 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 427K |
| 代理商： | M36LLR876B0 |
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
8/19
a negative transition of Chip Enable or Latch En-
able is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to
Table 8., Flash 1 and Flash 2 DC Charac-
teristics - Voltages
).
PSRAM Chip Enable input (E
P
).
The Chip En-
able input activates the PSRAM when driven Low
(asserted). When deasserted (V
IH
), the device is
disabled, and goes automatically in low-power
Standby mode or Deep Power-down mode.
P
).
Write Enable, W
P
,
controls the Bus Write operation of the PSRAM.
When asserted (V
IL
), the device is in Write mode
and Write operations can be performed either to
the configuration registers or to the memory array.
PSRAM Output Enable (G
P
). O
utput
G
P
, provides a high speed tri-state control, allow-
ing fast read/write cycles to be achieved with the
common I/O data bus.
Enable,
PSRAM Upper Byte Enable (UB
P
).
The Upper
Byte En-able, UB
P
, gates the data on the Upper
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LB
P
).
The Lower
Byte Enable, LB
P
, gates the data on the Lower
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
If both LB
P
and UB
P
are disabled (High) during an
operation, the device will disable the data bus from
receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active
mode as long as E
P
remains Low.
PSRAM Configuration Register Enable (CR
P
).
When this signal is driven High, V
IH
, Write opera-
tions load either the value of the Refresh Configu-
ration Register (RCR) or the Bus configuration
register (BCR).
V
DDF1
/V
DDF2
Supply Voltages.
V
DDF1
V
DDF2
provide the power supply to the internal
and
cores of Flash 1 and Flash 2, respectively. It is the
main power supply for all Flash memory opera-
tions (Read, Program and Erase).
V
CCP
Supply Voltage.
V
CCP
provides the power
supply to the internal core of the PSRAM device. It
is the main power supply for all PSRAM opera-
tions.
V
DDQF
Supply Voltage.
V
DDQF
power supply for the Flash memory. This allows all
Outputs to be powered independently of the Flash
memory and SRAM core power supplies, V
DDF
and V
CCP
.
provides
the
V
PPF
Program Supply Voltage.
V
PPF
is both a
control input and a power supply pin for the Flash
memories. The two functions are selected by the
voltage range applied to the pin.
If V
PPF
is kept in a low voltage range (0V to V
DDQF
)
V
PPF
is seen as a control input. In this case a volt-
age lower than V
PPLK
gives an absolute protection
against Program or Erase, while V
PPF
> V
PP1
en-
ables these functions (see Tables
6
and
8
, DC
Characteristics for the relevant values). V
PPF
is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If V
PPF
is in the range of V
PPH
it acts as a power
supply pin. In this condition V
PPF
must be stable
until the Program/Erase algorithm is completed.
V
SS
Ground.
V
SS
is the common ground refer-
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips. It must
be connected to the system ground.
Note: Each Flash memory device in a system
should have their supply voltage (V
DDF
) and
the program supply voltage V
PPF
decoupled
with a 0.1μF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca-
pacitors should be as close as possible to the
package). See
Figure 6., AC Measurement
Load Circuit
. The PCB track widths should be
sufficient to carry the required V
PPF
program
and erase currents.
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