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參數(shù)資料
| 型號： | M36P0R9070E0ZAC |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| 中文描述： | 512兆位（x16插槽，多銀行，多層次，多突發(fā)）128兆位閃存（突發(fā)）移動存儲芯片，1.8V電源，多芯片封裝 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大小： | 200K |
| 代理商： | M36P0R9070E0ZAC |
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M36P0R9070E0
2 Signal descriptions
11/26
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to
V
RPH
(refer to
Table 8., Flash Memory DC Characteristics - Voltages
).
2.11 PSRAM Chip Enable input (E
P
)
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(V
IH
), the device is disabled, and goes automatically in low-power Standby mode or Deep
Power-down mode.
2.12 PSRAM Write Enable (W
P
)
Write Enable, W
P
, controls the Bus Write operation of the PSRAM. When asserted (V
IL
), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13 PSRAM Output Enable (G
P
)
O
utput Enable, G
P
, provides a high speed tri-state control, allowing fast read/write cycles to be
achieved with the common I/O data bus.
2.14 PSRAM Upper Byte Enable (UB
P
)
The Upper Byte En-able, UB
P
, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.15 PSRAM Lower Byte Enable (LB
P
)
The Lower Byte Enable, LB
P
, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB
P
and UB
P
are disabled (High) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as E
P
remains Low.
2.16 PSRAM Configuration Register Enable (CR
P
)
When this signal is driven High, V
IH
, Write operations load either the value of the Refresh
Configuration Register (RCR) or the Bus configuration register (BCR).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36P0R9070E0ZACE | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| M36P0R9070E0ZACF | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36P0R9070E0ZACE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| M36P0R9070E0ZACF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36P0R9070E1ZACE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| M36P0R9070E1ZACF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36P0R9070N1ZSE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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