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參數(shù)資料
| 型號： | M36P0R9070E0ZAC |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| 中文描述： | 512兆位（x16插槽，多銀行，多層次，多突發(fā)）128兆位閃存（突發(fā)）移動存儲芯片，1.8V電源，多芯片封裝 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大小： | 200K |
| 代理商： | M36P0R9070E0ZAC |
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M36P0R9070E0
2 Signal descriptions
9/26
2
Signal descriptions
See
Table 1., Logic Diagram
and
Table 2., Signal Names
, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A24)
Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.
Addresses A23 and A24 are inputs for Flash memory components only. The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write
operations they control the commands sent to the Command Interface of the internal state
machine. The Flash memory is accessed through the Chip Enable signal (E
F
) and through the
Write Enable signal (W
F
), while the PSRAM is accessed through the Chip Enable signal (E
P
)
and the Write Enable signal (W
P
).
E
F
Low, and E
P
must not be Low at the same time.
2.2
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to
or from the upper part of the selected address when Upper Byte Enable (UB
P
) is driven Low.
The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the
selected address when Lower Byte Enable (LB
P
) is driven Low. When both UB
P
and LB
P
are
disabled, the Data Inputs/ Outputs are high impedance.
2.3
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash
memory.
2.4
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash memory.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36P0R9070E0ZACE | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| M36P0R9070E0ZACF | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| M36W0R6030B0 | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
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| M36W0R6030B0ZAQE | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36P0R9070E0ZACE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| M36P0R9070E0ZACF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36P0R9070E1ZACE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| M36P0R9070E1ZACF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36P0R9070N1ZSE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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