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參數(shù)資料
| 型號： | M36W0R6030B0ZAQ |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| 中文描述： | 64兆位（4Mb的x16插槽，多銀行，突發(fā)）閃存和8兆位（512KB的× 16）的SRAM，多芯片封裝 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 168K |
| 代理商： | M36W0R6030B0ZAQ |
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M36W0R6030T0, M36W0R6030B0
6/26
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
and
Table 1., Signal
Names
, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21).
Addresses
are common inputs for the Flash memory and the
SRAM components. The other lines (A19-A21) are
inputs for the Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the SRAM.
The Flash memory is accessed through the Chip
Enable signal (E
F
) and through the Write Enable
(W
F
) signal, while the SRAM is accessed through
two Chip Enable signals (E1
S
and E2
S
) and the
Write Enable signal (W
S
).
Data Input/Output (DQ0-DQ15).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (E
F
).
The Chip Enable in-
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low, V
IL
, and
Reset is High, V
IH
, the de-
vice is in active mode. When Chip Enable is at V
IH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Output Enable (G
F
).
The Output Enable
pin controls data outputs during Flash memory
Bus Read operations.
Flash Write Enable (
W
F
).
The
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
F
).
Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
IL
,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
IH
, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064FT/B datasheet).
Flash Reset (RP
F
).
The Reset input provides a
hardware reset of the memory. When Reset is at
V
IL
, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current I
DD2
. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
rents
for the value of I
DD2
. After Reset all blocks
A0-A18
Write
Enable
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at V
IH
, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to
Table 7., Flash Memory DC Characteris-
tics - Voltages
).
Flash Latch Enable (L
F
).
Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, V
IL
,
and it is inhibited when Latch Enable is High, V
IH
.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (K
F
).
The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V
IL
. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAIT
F
).
WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at V
IH
or Flash Reset is at V
IL
. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAIT
F
signal is not gated
by Output Enable.
SRAM Chip Enable inputs (E1
S
, E2
S
).
The
Chip Enable inputs activate the SRAM memory
control logic, input buffers and decoders. E1
S
at
V
IH
with E2
S
at V
IH
deselects the memory, reduc-
ing the power consumption to the standby level,
whereas E2
S
at V
IL
deselects the memory and re-
duces the power consumption to the Power-down
level, regardless of the level of E1
S
. E1
S
and E2
S
can also be used to control writing to the SRAM
memory array, while W
S
remains at V
IL.
It is not al-
lowed to set E
F
at V
IL,
E1
S
at V
IL
and E2
S
at V
IH
at
the same time.
SRAM Write Enable (W
S
).
The Write Enable in-
put controls writing to the SRAM memory array.
W
S
is active low.
SRAM Output Enable (G
S
).
The Output Enable
gates the outputs through the data buffers during
a Read operation of the SRAM memory. G
S
is ac-
tive low.
SRAM Upper Byte Enable (UB
S
).
The
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UB
S
is active low.
Upper
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36W0R6030B0ZAQE | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030B0ZAQF | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030B0ZAQT | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030T0 | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030T0ZAQ | 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36W0R6030B0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030B0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030B0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package |
| M36W0R6030T0ZAQ | 制造商:Micron Technology Inc 功能描述: |
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