參數(shù)資料
型號: M37150EFFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8.95 MHz, MICROCONTROLLER, PDSO42
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù): 100/142頁
文件大?。?/td> 1712K
代理商: M37150EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37150M6/M8/MA/MC/MF-XXXFP, M37150EFFP
59
Rev. 1.0
8.10.11 16-bit Shift Register
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. The contents of the high-order 8 bits of the stored caption data
can be obtained by reading out data register 2 (address 00E316) and
data register 4 (address 00CF16). The contents of the low-order 8
bits can be obtained by reading out data register 1 (address 00E216)
and data register 3 (address 00CE16), respectively. These registers
are reset to “0” at a falling edge of Vsep. Read out data registers 1
and 2 after the occurrence of a data slicer interrupt (refer to “8.10.12
Interrupt Request Generating Circuit”).
8.10.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 8.10.3 are generated by
combination of the following bits; bits 6 and 7 of the caption position
register (address 00E616). Read out the contents of data registers 1
to 4 and the contents of bits 3 to 7 of the clock run-in detect register
after the occurrence of a data slicer interrupt request.
Slice Line Specification Mode
CPS
Completion Flag 1
(bit 0 of DSC2)
Completion Flag 2
(bit 5 of CPS)
Caption Data
Registers 1, 2
Caption Data
Registers 3, 4
Line 21
A line specified by
bits 4 to 0 of CPS
Line 21
A line specified by
bits 4 to 0 of CPS
Invalid
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified
by bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified by
bits 4 to 0 of CPS
Invalid
16-bit data of a line specified by
bits 4 to 0 of CPS
Contents of Caption Data Latch Completion Flag
Contents of 16-bit Shift Register
bit 7
0
1
bit 6
0
1
0
1
CPS: Caption position register
DSC2: Data slicer control register 2
Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register
Caption position register
Occurence Souces of Interrupt Request at End of Data Slice Line
After slicing line 21
After a line specified by bits 4 to 0 of CPS
After slicing line 21
b7
0
1
b6
0
1
0
1
Table 8.10.3 Occurence Sources of Interrupt Request
相關(guān)PDF資料
PDF描述
M37150M8-XXXFP 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42
M37150MF-XXXFP 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42
M37150MC-XXXFP 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42
M37151MC-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
M37151MF-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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