參數(shù)資料
型號(hào): M37150EFFP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8.95 MHz, MICROCONTROLLER, PDSO42
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁(yè)數(shù): 54/142頁(yè)
文件大?。?/td> 1712K
代理商: M37150EFFP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37150M6/M8/MA/MC/MF-XXXFP, M37150EFFP
MITSUBISHI MICROCOMPUTERS
18
Rev. 1.0
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8.3 INTERRUPTS
Interrupts can be caused by 17 different sources comprising 4 exter-
nal, 11 internal, 1 software, and 1 reset interrupts. Interrupts are vec-
tored interrupts with priorities as shown in Table 8.3.1. Reset is also
included in the table as its operation is similar to an interrupt.
When an interrupt is accepted,
The contents of the program counter and processor status regis
ter are automatically stored into the stack.
The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
The jump destination address stored in the vector address enters
the program counter. Other interrupts are disabled when the in
terrupt disable flag is set to “1.”
All interrupts except the BRK instruction interrupt have an inter
rupt request bit and an interrupt enable bit. The interrupt request
bits are in Interrupt Request Registers 1 and 2 and the interrupt
enable bits are in Interrupt Control Registers 1 and 2. Figures
8.3.2 to 8.3.6 show the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1,” interrupt request bit
is “1,” and the interrupt disable flag is “0.” The interrupt request
bit can be set to “0” by a program, but not set to “1.” The interrupt
enable bit can be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest pri
ority.
Figure 8.3.1 shows interrupt controls.
8.3.1 Interrupt Causes
(1)VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal. The OSD interrupt occurs after charac-
ter block display to the CRT is completed.
(2)INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs; the sys-
tem detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The in-
put active edge can be selected by bits 0 to 2 of the Interrupt
Input Polarity Register (address 00DC16); when this bit is “0,” a
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
(3)Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
(4)Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
Vector Addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Interrupt Source
Reset
OSD interrupt
INT1 external interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
INT3 external interrupt
INT2 external interrupt
Multi-master I2C-BUS interface interrupt
Timer 5 6 interrupt
BRK instruction interrupt
Remarks
Non-maskable
Active edge selectable
Source switch by software (see note)
Non-maskable
Table 8.3.1 Interrupt Vector Addresses and Priority
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
相關(guān)PDF資料
PDF描述
M37150M8-XXXFP 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42
M37150MF-XXXFP 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42
M37150MC-XXXFP 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42
M37151MC-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
M37151MF-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
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