參數(shù)資料
型號: M37151
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 70/139頁
文件大小: 1491K
代理商: M37151
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
69
Rev 1.0
Fig. 8.11.10 Block Diagram of Dot Size Control Circuit
Fig. 8.11.11 Definition of Dot Sizes
1 dot
Scanning line of F1(F2 )
Scanning line of F2(F1 )
1/2 H
1H
2H
3H
3T
C
2T
C
1T
C
1T
C
Data slicer clock
H
SYNC
f (OSC)
OC3 or OC4
Synchronous
circuit
Pre-divide circuit
Clock cycle
= 1T
C
Cycle
2
0
Cycle
3
1
BCi4
Note:
To use data slicer clock, set bit 0 of data slicer control register 1 to 1.
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
0
1
OC7
8.11.2 Dot Size
The dot size can be selected in block units. The vertical dot size is
determined by dividing H
SYNC
in the vertical dot size control circuit.
The horizontal dot size is determined by dividing the following clock
in the horizontal dot size control circuit : the clock gained by dividing
the OSD clock source (data slicer clock, f (OSC) in the pre-divide
circuit. The clock cycle divided in the pre-divide circuit is defined as
1T
C
.
The dot size of each block is specified by bits 2 to 4 of block control
register i.
Refer to Figure 8.11.4 for the structure of the block control register.
The block diagram of the dot size control circuit is shown in Figure
8.11.10.
The pre-divide ratio is specified by bit 7 of the OSD control register
(address 00D0
16
) and bit 4 of block control register i (addresses
00D2
16
and 00D3
16
) .
When bit 7 of the OSD control register (address 00D0
16
) is set to
"0," the double or triple pre-divide ratio can be chosen per block unit
by bit 4 of block control register i. And then, when it is set to "1", the
pre-divide ratio increases 1 time (both blocks 1 and 2). The pre-di-
vided dot size can be specified per block unit by bits 2 and 3 of block
control register i.
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