參數(shù)資料
型號(hào): M37151
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù): 8/139頁(yè)
文件大?。?/td> 1491K
代理商: M37151
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
7
Rev 1.0
Pin
Name
Input/
Output
Functions
V
CC
, V
SS
CNV
SS
RESET
Power source
CNV
SS
Reset input
Apply voltage of 5 V ± 10 % to (typical) V
CC
, and 0 V to V
SS
.
This is connected to V
SS
.
To enter the reset state, the reset input pin must be kept at a LOW for 2 ms or more (under
normal V
CC
conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
This is the input pin for the main clock generating circuit. Built-in clock clock generation
circuit, when set
to oscillation frequency, connect ceramic resonator or crystal frequency between X
IN
and
X
OUT
. When use external clock input, connect clock oscillation source to X
IN
pin, and open
X
OUT
pin.
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. (See note)
Output Pins P00 to P04 are also used as PWM output pins PWM0 to PWM4, respectively.
The output structure is N-channel open-drain output.
Pins P0
6
and P0
7
are also used as INT external interrupt input pins INT2 and INT1 respectively.
Input
X
IN
Clock input
Input
X
OUT
Clock output
Output
P0
0
/PWM0–
P0
2
/PWM2,
P03/PWM3/AD1,
I/O port P0
I/O
P0
4
/PWM4/AD2,
P0
5
/AD3,
PWM output
Output
P0
6
/INT2/AD4,
P0
7
/INT1
External interrupt
input
Analog input
Input
Input
Pins P0
3,
P0
4,
P0
5
and P0
6
are also used as analog input pins AD1, AD2, AD3 and AD4,
respectively.
Port P1 is a 7-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note)
Pins P1
1
–P1
4
are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I
2
C-BUS interface is used. The output structure is N-channel open-drain output.
P1
0
pin is also used as Clock control output CLK CONT. The output structure is CMOS
output.
External clock
Input
P1
6
pin is also used as timer external clock input pin TIM2.
input for timer
P1
0
/CLK CONT,
I/O port P1
P1
1
/SCL1,
P1
2
/SCL2,
P1
3
/SDA1,
P1
4
/SDA2,
P1
5
,
P1
6/
AD8
/
TIM2
I/O
Multi-master
I
2
C-BUS interface
Clock control
I/O
Output
Analog input Input
P1
6
pin is also used as analog input pin AD8.
P2
0
/S
CLK
/AD5,
P2
1
/S
OUT
/AD6,
P2
2
/S
IN
/AD7,
P2
3
/TIM3,
P2
4
/TIM2,
P2
5
/INT3,
P2
6
/
X
CIN
,
P27/X
COUT
I/O port P2
I/O
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note)
Serial I/O synchronous
clock input/output port
Serial I/O data
output
Serial I/O data input
External clock
input for timer
Analog input
Sub-clock input
Sub-clock output
External interrupt
input
I/O port P3
I/O
P2
0
pin is also used as serial I/O synchronous clock input/output pin S
CLK
. The output
structure is N-channel open-drain output.
P2
1
pin is also used as serial I/O data output pin S
OUT
. The output structure is open-drain
output.
P2
2
pin is also used as serial I/O data input pin S
IN
.
Pins P2
3
and P2
4
are also used as timer external clock input pins TIM3 and TIM2
respectively.
Pins P2
0
–P2
2
are also used as analog input pins AD5, AD6 and AD7 respectively.
P2
6
pin is also used as sub-clock input pin X
CIN
.
P2
7
pin is also used as sub-clock output pin X
COUT
. The output structure is CMOS output.
P2
5
pin is also used as INT external interrupt input pin INT3.
Output
Input
Input
Input
Input
Output
Input
P3
0
/SDA3
P3
1
/SCL3
I/O
Port P3
0
,P3
1
is an 2-bit I/O port and has basically the same functions as port P0.
The output structure is CMOS output. (See note)
Multi-master I/O Pins P3
0
,P3
1
are used as SDA3,SCL3 respectively, when multi-master I
2
C-BUS
I
2
C-BUS Interface interface is used. The output structure is N-channel open-drain output.
7. PIN DESCRIPTION
Table 7.1 PIN DESCRIPTION
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