參數(shù)資料
型號(hào): M37207M8-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64
封裝: 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁(yè)數(shù): 90/124頁(yè)
文件大?。?/td> 1993K
代理商: M37207M8-XXXSP
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MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
65
Fig. 60. Display Counter
Fig. 61. Timing of CRT Interrupt Request and Display Counter Value
The display block counter counts the number of times the display of
a block has been completed, and its contents are incremented by 1
each time the display of one block is completed.
To provide multi-line display, enable CRT interrupts by clearing the
interrupt disable flag to “0” and setting the CRT interrupt enable bit
(bit 4 of address 00FE16) to “1.” After that, process the following
sequence within the CRT interrupt processing routine:
ead the value of the display block counter.
The block for which display is terminated (i.e., the cause of CRT
interrupt generation) can be determined by the value read in
.
Replace the display character data and vertical display position of
that block with the character data (contents of CRT display RAM)
and vertical display position (contents of vertical position register)
to be displayed next.
Figure 60 shows the structure of the display block counter.
0
Block 1
Block 2
Count value
Block 3
Block 1’
1
2
3
4
Interrupt position
b7 b6 b5 b4 b3 b2 b1 b0
Display block counter (CBC) [Address 00EB 16]
B
Name
Functions
After reset
R W
Display Block Counter
0
to
3
Number of blocks which are being displayed or has
displayed
(Incremented each time a block is displayed)
Indeterminate RW
0
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
R—
4
to
7
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PDF描述
M37207MF-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64
M37210M3-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PQFP64
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