參數(shù)資料
型號(hào)： M37210M3-800SP
廠商： Mitsubishi Electric Corporation
英文描述： TRANS PREBIASED PNP 200MW SOT-23
中文描述： 單芯片8位CMOS微機(jī)電壓合成與屏幕顯示控制器
文件頁(yè)數(shù)： 35/59頁(yè)
文件大?。?/td> 764K
代理商： M37210M3-800SP
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
35
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The M37210M3-XXXSP incorporates an interrupt interval determina-
tion circuit. This interrupt interval determination circuit has an 8-bit
binary up counter as shown in Figure 34.
Using this counter, it determines an interval or a pulse width on the
INT1 or INT2 (refer to Figure 36).
The following describes how the interrupt interval is determined.
1. The interrupt input to be determined (INT1 input or INT2 input) is
selected by using bit 2 in the interrupt interval determination con-
trol register (address 00D8
16
). When this bit is cleared to “0”, the
INT1 input is selected ; when the bit is set to “1”, the INT2 input is
selected.
2. When the INT1 input is to be determined, the polarity is selected
by using bit 3 of the interrupt interval determination control regis-
ter ; when the INT2 input is to be determined, the polarity is se-
lected by using bit 4 of the interrupt interval determination control
register.
When the relevant bit is cleared to “0”, determination is made of
the interval of a positive polarity (rising transition) ; when the bit is
set to “1”, determination is made of the interval of a negative po-
Fig. 34 Block diagram of interrupt interval determination circuit
Note : The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles.
Data bus
RE
1
INT1
(Note)
RE
0
RE
2
INT2
32
μ
s
8
8
8-bit binary up counter
Interrupt interval determination register
64
μ
s
Address 00D7
16
Control
circuit
Selection gate : Connected to black
colored side at reset.
RE : Interrupt interval determination control register
larity (falling transition).
3. The reference clock is selected by using bit 1 of the interrupt inter-
val determination control register. When the bit is cleared to “0”, a
64
m
s clock is selected ; when the bit is set to “1”, a 32
μ
s clock is
selected (based on an oscillation frequency of 4MHz in either
case).
4. Simultaneously when the input pulse of the specified polarity (ris-
ing or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-
bit binary up counter starts counting up with the selected
reference clock (64
μ
s or 32
μ
s).
5. Simultaneously with the next input pulse, the value of the 8-bit bi-
nary up counter is loaded into the determination register (address
00D7
16
) and the counter is immediately reset (00
16
). The refer-
ence clock is input in succession even after the counter is reset,
and the counter restarts counting up from “00
16
”.
6. When count value “FE
16
” is reached, the 8-bit binary up counter
stops counting. Then, simultaneously when the next reference
clock is input, the counter sets value “FF
16
” to the determination
register.
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