參數(shù)資料
型號： M37210M3-800SP
廠商： Mitsubishi Electric Corporation
英文描述： TRANS PREBIASED PNP 200MW SOT-23
中文描述： 單芯片8位CMOS微機(jī)電壓合成與屏幕顯示控制器
文件頁數(shù)： 42/59頁
文件大小： 764K
代理商： M37210M3-800SP
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
42
CLOCK GENERATING CIRCUIT
The built-in clock generating circuit is shown in Figure 44.
When the STP instruction is executed, the internal clock
φ
stops os-
cillating at “H” level. At the same time, timers 3 and 4 are connected
in hardware and “FF
16
” is set in the timer 3, “07
16
” is set in the timer
4. Select f(X
IN
)/16 as the timer 3 count source (set bit 0 of the timer
34 mode register to “0” before the execution of the STP instruction).
And besides, set the timer 3 and timer 4 interrupt enable bits to dis-
abled (“0”) before execution of the STP instruction.
The oscillator is restarted when an external interrupt is accepted.
However, the internal clock
φ
keeps its “H” level until timer 4 over-
flows.
This is because the oscillator needs a set-up period if a ceramic reso-
nator or a quartz-crystal oscillator is used.
When the WIT instruction is executed, the internal clock
φ
stops in the
“H” level but the oscillator continues running. This wait state is
cleared when an interrupt is accepted (Note). Since the oscillation
does not stop, the next instructions are executed at once.
To return from the stop or the wait state, set the interrupt enable bit to
“1” before executing the STP or the WIT instruction.
Note :
In the wait mode, the following interrupts are invalid.
(1) V
SYNC
interrupt
(2) CRT interrupt
(3) Timer 2 interrupt using P3
2
/TIM2 pin input as count source
(4) Timer 3 interrupt using P3
3
/TIM3 pin input as count source
(5) Timer 4 interrupt using f(X
IN
)/2 as count source
The circuit example using a ceramic resonator (or a quartz crystal
oscillator) is shown in Figure 42.
Use the circuit constants in accordance with the resonator
manufacture’s recommended values.
Fig. 44 Clock generating circuit block diagram
Interrupt request
Interrupt
disable flag I
Reset
S
Q
R
S
Q
R
S
Q
R
Reset
STP instruction
Timer 4
Timer 3
1/2
1/8
Internal clock
φ
TIM3
T34M
2
T34M
0
X
IN
X
OUT
WIT
instruction
STP instruction
Selection gate: Connected to black
colored side at reset.
Fig. 42 Ceramic resonator circuit example
Fig. 43 External clock input circuit example
M37210M3-XXXSP
X
IN
24
X
OUT
25
C
IN
C
OUT
M37210M3-XXXSP
X
IN
External oscillation
circuit
Vcc
Vss
24
The example of external clock usage is shown in Figure 43 X
IN
is the
input, and X
OUT
is open.
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