參數(shù)資料
型號(hào)： M37270MF-100SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 6/94頁
文件大?。?/td> 1551K
代理商： M37270MF-100SP
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
6
Input
Input
Output
I/O
Output
I/O
Output
Output
Input
I/O
Input
I/O
Output
Input
Input
Input
Input
Output
I/O
Output
Output
Output
Output
Apply voltage of 5 V ± 10 % (typical) to V
CC
and AV
CC
, and 0 V to V
SS
.
This is connected to V
SS
.
To enter the reset state, the reset input pin must be kept at a “L” for 2
μ
s or more (under
normal V
CC
conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins X
IN
and
X
OUT
. If an external clock is used, the clock source should be connected to the X
IN
pin and
the X
OUT
pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
of P0
3
is CMOS output, that of P0
0
–P0
2
and P0
4
–P0
7
are N-channel open-drain output.
The note out of this Table gives a full of port P0 function.
Pins P0
0
–P0
2
and P0
4
–P0
7
are also used as PWM output pins PWM4–PWM6 and PWM0–
PWM3 respectively. The output structure is N-channel open-drain output.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P1
0
and P1
5
–P1
7
is CMOS output, that of P1
1
–P1
4
is N-channel open-drain
output.
Pins P1
0
, P1
5
, P1
6
are also used as OSD output pins OUT2, I1, I2 respectively. The output
structure is CMOS output.
Pins P1
1
–P1
4
are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I
2
C-BUS interface is used. The output structure is N-channel open-drain output.
P1
7
pin is also used as serial I/O data input pin S
IN
.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P2
4
–P2
6
are also used as analog input pins AD3–AD1 respectively.
Ports P3
0
and P3
1
are a 2-bit I/O port and has basically the same functions as port P0. The
output structure is CMOS output.
Port P3
2
is a 1-bit output port. The output structure is N-channel open-drain output.
Ports P4
0
–P4
6
are a 7-bit input port.
P4
0
pin is also used as analog input pin AD4.
Pins P4
1
, P4
4
are also used as external interrupt input INT2, INT1.
Pins P4
2
and P4
3
are also used as external clock input pins TIM2, TIM3 respectively.
P4
5
pin is used as serial I/O data output pin S
OUT
. The output structure is N-channel open-
drain output.
P4
6
pin is used as serial I/O synchronizing clock input/output pin S
CLK
. The output struc-
ture is N-channel open-drain output.
Port P4
7
is a 1-bit output port. The output structure is N-channel open-drain output.
Ports P5
0
–P5
7
are an 8-bit output port. The output structure of P5
0
, P5
1
, P5
6
, P5
7
are N-
channel open-drain output, that of P5
2
–P5
5
is CMOS output.
P5
0
pin is also used as PWM output pin PWM7.
Pins P5
2
–P5
5
are also used as OSD output pins R, G, B, OUT1 respectively.
PIN DESCRIPTION
Pin
Name
Functions
Input/
Output
Power source
CNV
SS
Reset input
Clock input
Clock output
I/O port P0
PWM output
I/O port P1
OSD output
Multi-master
I
2
C-BUS interface
Serial I/O data
input
I/O port P2
Analog input
I/O port P3
Output port P3
Input port P4
Analog input
External interrupt
input
External clock input
Serial I/O data
output
Serial I/O
synchronizing clock
input/output
Output port P4
Output port P5
PWM output
OSD output
V
CC
,
AV
CC
,
V
SS.
CNV
SS
RESET
X
IN
X
OUT
P0
0
/PWM4–
P0
2
/PWM6,
P0
3,
P0
4
/PWM0–
P0
7
/PWM3
P1
0
/OUT2,
P1
1
/SCL1,
P1
2
/SCL2,
P1
3
/SDA1,
P1
4
/SDA2,
P1
5
/I1,
P1
6
/I2/INT3,
P1
7
/S
IN
P2
0
–P2
3
P2
4
/AD3–
P2
6
/AD
1,
P2
7
P3
0
, P3
1
P3
2
P4
0
/AD4,
P4
1
/INT2,
P4
2
/TIM2,
P4
3
/TIM3,
P4
4
/INT1,
P4
5
/S
OUT
,
P4
6
/S
CLK
,
P4
7
P5
0
/PWN7,
P5
1
, P5
2
/R,
P5
3
/G, P5
4
/B,
P5
5
/OUT1,
P5
6
, P5
7
相關(guān)PDF資料
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