參數(shù)資料
型號: M37270MF-101SP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 17/94頁
文件大小: 1551K
代理商: M37270MF-101SP
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
17
SERIAL I/O
The M37270MF-XXXSP has a built-in serial I/O which can either trans-
mit or receive 8-bit data in serial in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 9. The synchronizing
clock I/O pin (S
CLK
), and data output pin (S
OUT
) also function as port
P4, data input pin (S
IN
) also functions as port P1.
Bit 2 of the serial I/O mode register (address 0213
16
) selects whether
the synchronizing clock is supplied internally or externally (from the
P4
6
/S
CLK
pin). When an internal clock is selected, bits 1 and 0 select
whether f(X
IN
) or f(X
CIN
) is divided by 8, 16, 32, or 64. To use P4
5
/
S
OUT
and P4
6
/S
CLK
pins for serial I/O, set the corresponding bits of
the port P4 direction register (address 00C9
16
) to “0.” To use P1
7
/S
IN
pin for serial I/O, set the corresponding bit of the port P1 direction
register (address 00C3
16
) to “0.”
Fig. 9. Serial I/O block diagram
The operation of the serial I/O function is described below. The func-
tion of the serial I/O differs depending on the clock source; external
clock or internal clock.
8
Serial I/O shift register (8)
Data bus
Serial I/O
interrupt request
Selection gate: Connect to
black colored
side at reset.
Synchronization
circuit
Frequency divider
1/4
1/2
1/8
1/16
SM
1
SM
0
Serial I/O counter (8)
SM
5
: LSB
MSB
S
SM
2
1/2
X
IN
P1
7
/S
IN
P4
5
/S
OUT
P4
6
/S
CLK
1/2
(Address 0214
16
)
X
CIN
1/2
CM
7
Note :
When the data is set in the serial I/O register (address 0214
16
), the register functions as the serial I/O shift register.
(Note)
CM : CPU mode register
SM : Serial I/O mode register
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