參數(shù)資料
型號(hào): M37270MF-101SP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù): 35/94頁(yè)
文件大?。?/td> 1551K
代理商: M37270MF-101SP
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
35
Fig. 34. Sync pulse counter register
Sync pulse counter register
(SYC : address 00EA
16
)
Count value
Count source
Count time
0: H
SYNC
signal
1: Composite
sync signal
f(X
IN
)/2
13
(1024
s, f(X
IN
) = 8 MHz)
7
0
(12) Synchronizing Signal Counter
The synchronizing signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronizing signal V
sep
as a count source.
The count value in a certain time (T time) generated by f(X
IN
)/2
13
or
f(X
IN
)/2
13
is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F
16
,”
“1F
16
” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 00EA
16
). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronizing signal counter is used when bit 0 of the PWM
mode register 1 (address 02EA
16
).
Figure 34 shows the structure of the sync pulse counter and Figure
35 shows the synchronizing signal counter block diagram.
Fig. 35. Synchronizing signal counter block diagram
Reset
5-bit counter
Latch (5 bits)
f(X
IN
)/2
13
Composite
sync signal
H
SYNC
signal
Counter
Sync pulse
counter register
Data bus
Selection gate : connected to black
colored side when
reset.
b5
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