參數(shù)資料
型號: M37480M2T-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-32
文件頁數(shù): 15/100頁
文件大小: 1457K
代理商: M37480M2T-XXXSP
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
18
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Table 4. Interrupt vector addresses and priority
At reset
At detection of either rising edge or falling
edge of INT0 input
At detection of either rising edge or falling
edge of INT1 input
At input “L” to port P0 in key-on wake-up
mode
At detection of either rising edge or falling
edge of CNTR0 input
At detection of either rising edge or falling
edge of CNTR1 input
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O data reception
At completion of serial I/O transfer shift or
when transmission buffer is empty
At detection of bus collision
At completion of A-D conversion
At execution of BRK instruction
Non-maskable
External interrupt
(active edge programmable)
External interrupt
(active edge programmable)
Validity after execution of
STP/WIT instruction
External interrupt
(active edge programmable)
External interrupt
(active edge programmable)
Non-maskable software
interrupt
RESET (Note 2)
INT0
INT1
Key-on wake-up
CNTR0
CNTR1
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O reception
Serial I/O transmission
Bus arbitration
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Interrupt source
Prior-
ity
Vector address (Note 1)
High-order Low-order
Interrupt request generating conditions
Remarks
FFFF16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFFE16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : RESET is mentioned in the table because its operation is the same as an interrupt.
Fig. 15 Interrupt control diagram
Interrupt request bit
Interrupt enable bit
Interrupt disable flag
BRK instruction
Reset
Interrupt request
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