參數(shù)資料
型號: M37480M2T-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-32
文件頁數(shù): 36/100頁
文件大?。?/td> 1457K
代理商: M37480M2T-XXXSP
37
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
A-D Converter
For A-D conversion, the 8-bit successive comparison method is
used. Figure 38 shows a block diagram of A-D conversion. Con-
version is automatically performed once started by the program.
There are 8 analog input pins that are in common with P27 to P20
of port P2 (4 pins of P23 to P20 in the 7480 group).
Pin inputs to be A-D converted are selected by bit 2 to bit 0 of the
A-D control register (address 00D916). Bit 3 of the A-D control reg-
ister is an A-D conversion completion bit. This bit is “0” during A-D
conversion and “1” after completion of it. Accordingly, it is possible
by checking this bit to know whether A-D conversion is completed
or not. Figure 39 shows the relationship between the contents of
the A-D control register and input pins to be selected.
The A-D conversion register (address 00DA16) stores conversion
results, so it is possible to know them by reading the contents of
this register.
Next, the procedure for executing A-D conversion will be ex-
plained below. First, set values in bit 2 to bit 0 of the A-D control
register and select pins to be A-D converted.
Next, clear the A-D conversion completion bit to “0”. With this write
operation, A-D conversion is started. The A-D conversion is com-
pleted after the lapse of 50 machine cycles (12.5
s at f(XIN)= 8
MHz), and the A-D conversion completion bit is set to “1”. The A-D
conversion interrupt request bit is also set to “1”. Conversion re-
sults are stored in the A-D conversion register.
Fig. 38 Block diagram of A-D converter circuit
Comparator
A-D control circuit
A-D conversion register
(address 00DA16)
Switch tree
Ladder resistor
A-D conversion
completion
interrupt request
VSS (Note 1)
VREF
1 : AVSS for the 44P6N package of the 7481 group.
2 : The 7480 group is not provided with P2 4/IN4 to P27/IN7.
P20/IN0
P21/IN1
P22/IN2
P23/IN3
P24/IN4
P25/IN5
P26/IN6
P27/IN7
Data bus
A-D control register
(address 00D916)
b4
b0
Channel
selector
Notes
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