參數(shù)資料
型號： M37516E6HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 42/90頁
文件大?。?/td> 1144K
代理商： M37516E6HP
Rev.1.01
Jul 01, 2003
page 47 of 89
7516 Group
Fig. 54 Structure of MISRG
sNotes on middle-speed mode automatic
switch set bit
When the middle-speed mode automatic switch set bit is set to “1”
while operating in the low-speed mode, by detecting the rising/fall-
ing edge of the SCL or SDA pin, XIN oscillation automatically starts
and the mode is automatically switched to the middle-speed
mode. The timing which changes from the low-speed mode to the
middle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5
cycle in the low-speed mode by the middle-speed mode automatic
switch waiting time set bit. Select according to the oscillation start
characteristic of the XIN oscillator to be used.
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 003816)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
b7
b0
Notes 1: While operating in the low-speed mode, the mode can be automatically
switched to the middle-speed mode by the SCL/SDA interrupt.
2: When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address
003B16) changes.
Not used (return “0” when read)
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start (Note 2)
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable (Notes 1, 2)
WIT instruction
STP instruction
Timing
φ (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2
1/4
XIN
XOUT
XCOUT
XCIN
Interrupt request
Reset
Interrupt disable flag l
1/2
Port XC
switch bit
“1”
“0”
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: When bit 0 of MISRG = “0”
Main clock division ratio
selection bits (Note 1)
FF16
0116
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
Reset
Timer 12 count source
selection bit
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