參數(shù)資料
型號(hào)： M37534E8SP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 41/55頁(yè)
文件大?。?/td> 610K
代理商： M37534E8SP
7534 Group
Rev.2.00
Jun 21, 2004
page 46 of 54
REJ03B0099-0200Z
Differences among 32-pin, 36-pin and 42-pin
The 7534 Group has three package types, and each of the number
of I/O ports are different. Accordingly, when the pins which have the
function except a port function are eliminated, be careful that the
functions are also eliminated.
Table 15 Differences among 32-pin, 36-pin and 42-pin
I/O port
Port P1
Port P2
Port P3
Port P4
42-pin SDIP
P10–P16 (7-bit structure)
P20–P27 (8-bit structure)
(A/D converter 8-channel)
P30–P37 (8-bit structure)
(INT0, INT1 available)
P40, P41 (2-bit structure)
36-pin SSOP
P10–P14 (5-bit structure)
P20–P27 (8-bit structure)
(A/D converter 8-channel)
P30–P35, P37 (7-bit structure)
(INT0 available)
No port
32-pin LQFP
P10–P14 (5-bit structure)
P20–P25 (6-bit structure)
(A/D converter 6-channel)
P30–P34 (5-bit structure)
(INT function not available)
No port
Description of improved USB function for 7534
Group
Table 14 Description of improved USB function for 7534 Group
No.
1
2
3
4
5
Parameter
Response at Control transfer
D+/D- transceiver circuit
Power dissipation at Suspend
STALL in Status stage
6-bit decode of SYNC field
7532/7536 Group
Not deal with the host which performs the Control
transfer in parallel to plural device.
USB function can be used only at the condition of
CL = 150 pF to 350 pF.
Rating is Max. 300
A not including the output cur-
rent of USBVREFOUT.
ACK is returned once to OUT (DATA0) to be valid
in Status stage.
SYNC is detected only when 8-bit full code (8016)
is complete.
7534 Group
Connectable to the host which performs the Con-
trol transfer in parallel to plural device.
Deal with the the following USB Spefification Rev.
1.1.
CL = 200 pF to 450 pF,
Trise and Tfall: 75 ns to 300 ns,
Tr/Tf: 80 % to 125 %,
Cross over Voltage: 1.3 V to 2.0 V.
Rating is Max. 300
A including the output current
of USBVREFOUT, by low-power dissipation of D+/
D- input circuit and 3.3 V-regulator.
STALL is set automaticcally by hardware when
OUT (DATA0) is received in Status stage.
SYNC is detected only the low-order 6 bits even if
the high-order 2 bits are corrupted.
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