參數(shù)資料
型號: M37542M2T-XXXGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 122/139頁
文件大?。?/td> 1448K
代理商: M37542M2T-XXXGP
7542 Group
Rev.3.02
Oct 31, 2006
Page 83 of 134
REJ03B0006-0302
● Parallel I/O Mode
The parallel I/O mode is used to input/output software commands,
address and data in parallel for operation (read, program and
erase) to internal flash memory.
Use the external device (writer) only for 7542 Group (flash
memory version). For details, refer to the user’s manual of each
writer manufacturer.
User ROM and Boot ROM Areas
In parallel I/O mode, the User ROM and Boot ROM areas shown
in Figure 94 can be rewritten. Both areas of flash memory can be
operated on in the same way.
The Boot ROM area is 4 Kbytes in size and located at addresses
F00016 through FFFF16. Make sure program and block erase op-
erations are always performed within this address range. (Access
to any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the fac-
tory. Therefore, using the MCU in standard serial I/O mode, do not
rewrite to the Boot ROM area.
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