參數(shù)資料
型號： M37544G2GP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù)： 15/70頁
文件大小： 645K
代理商： M37544G2GP
7544 Group
Rev.1.04
2004.06.08
page 20 of 66
REJ03B0012-0104Z
Fig. 19 Interrupt control
Fig. 20 Structure of Interrupt-related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7
b0
b7
b0
b7
b0
Interrupt edge selection register
INT0 interrupt edge selection bit
(INTEDGE : address 003A16, initial value : 0016)
Interrupt request register 1
Serial I/O receive interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16, initial value : 0016)
b7
b0 Interrupt control register 1
Serial I/O receive interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
(ICON1 : address 003E16, initial value : 0016)
Interrupt request register 2
Disable (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ2 : address 003D16, initial value : 0016)
b7
b0 Interrupt control register 2
Disable (returns “0” when read)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16, initial value : 0016)
(Do not write “1” to this bit)
Disable (returns “0” when read)
Timer 1 interrupt enable bit
A/D conversion interrupt enable bit
Disable (returns “0” when read)
Timer A interrupt enable bit
Disable (returns “0” when read)
Timer X interrupt enable bit
CNTR1 interrupt enable bit
CNTR0 interrupt enable bit
Key-on wake up interrupt enable bit
INT1 interrupt enable bit
INT0 interrupt enable bit
Serial I/O transmit interrupt enable bit
Disable (returns “0” when read)
Timer 1 interrupt request bit
A/D conversion interrupt request bit
Disable (returns “0” when read)
Timer A interrupt request bit
Disable (returns “0” when read)
Timer X interrupt request bit
CNTR1 interrupt request bit
CNTR0 interrupt request bit
Key-on wake up interrupt request bit
INT1 interrupt request bit
INT0 interrupt request bit
Serial I/O transmit interrupt request bit
1 : Key-on wakeup disabled
0 : Key-on wakeup enabled
P00 key-on wakeup enable bit
Disable (returns “0” when read)
1 : Rising edge active
0 : Falling edge active
INT1 interrupt edge selection bit
1 : Rising edge active
0 : Falling edge active
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