REJ03B0156-0122
Rev.1.22
Mar 31, 2009
page 52 of 94
7547 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
● Standard operation of watchdog timer
(1) Start of watchdog timer
The watchdog timer starts operating by setting value of the func-
tion set ROM data 2 (FSROM2: address 0FFA16) or writing to the
watchdog timer control register (WDTCON: address 003916).
Set “0” to the watchdog timer start selection bit (bit 1 of FSROM2)
when operation starts by setting value of FSROM2. In this case,
the watchdog timer starts operating after releasing reset.
Write an arbitrary value to WDTCON when FSROM2 is set to be
invalid and operation starts by program. Operation by program
can start even when “1” (stop state after releasing reset) is set to
the watchdog timer start selection bit.
(2) Operation of watchdog timer
Watchdog timer L is set to “FF16”and watchdog timer H is set to
“FF16” by reset or writing an arbitrary value to WDTCON.
When the watchdog timer starts operating, the selected clock is
counted and internal reset occurs by the watchdog timer H under-
flow.
Accordingly, write to WDTCON before underflow by program.
When WDTCON is read, the values of the STP instruction function
selection bit, watchdog timer H count source selection bit and the
high-order 6 bits of the watchdog timer H are read.
(3) Count source clock of watchdog timer
The count source clock of the watchdog timer can be selected by
the watchdog timer source clock selection bit (bit 0 of FSROM2).
If “0” is set to the watchdog timer source clock selection bit, the
count source clock of the watchdog timer always is the on-chip os-
cillator output/16.
It changes by setting the clock division ratio selection bits (bit 7
and bit 6 of the CPU mode register) when “1” is set to the watch-
dog timer source clock selection bit or FSROM2 is set to be
invalid.
When a double-speed mode, a high-speed mode, and a middle-
speed mode are selected by the clock division ratio selection bits,
the count source clock of the watchdog timer becomes f(XIN)/16.
When the supply from on-chip oscillator is selected, it becomes
the on-chip oscillator output/16.
(4) Watchdog timer H count source selection bit
The count source of watchdog timer H can be selected by
FSROM2 or program.
When “0” is set to watchdog timer H count source selection bit (bit
2 of FSROM2), the watchdog timer L underflow signal is selected
as the count source of watchdog timer H and the detection time is
131.072 ms at f(XIN) = 8 MHz.
When “1” is set to this bit, the clock selected as the count source
of watchdog timer L is input to watchdog timer H. In this case, the
detection time is 512 s at f(XIN) =8 MHz.
When FSROM2 is set to be invalid, the count source of watchdog
timer can be set by watchdog timer H count source selection bit
(bit 7 of WDTCON).
When “0” is set to this bit, the watchdog timer L underflow signal is
selected as the count source of watchdog timer H.
When “1” is set to this bit, the clock selected as the count source
of watchdog timer L is input to watchdog timer H.
This bit is cleared to “0” after reset.
(5) STP instruction function selection bit
The function of the STP instruction can be selected by FSROM2
or program.
When “0” is set to the STP instruction function selection bit (bit 3
of FSROM2), system enters into the stop mode at the STP instruc-
tion execution.
When “1” is set to this bit, internal reset occurs at the STP instruc-
tion execution. When the function of the STP instruction is set by
FSROM2, it cannot be changed by program.
When setting value of FSROM2 is invalid, the function of the STP
instruction can be set by the STP instruction function selection bit
(bit 6 of WDTCON).
When “0” is set to this bit, system enters into the stop mode at the
STP instruction execution.
When “1” is set to this bit, internal reset occurs at the STP instruc-
tion execution.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
■ Notes on watchdog timer
1. The watchdog timer is operating during the wait mode. Write
data to the watchdog timer control register to prevent timer un-
derflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the oscillation stabilizing time
after the STP instruction is released. In order to avoid the un-
derflow of the watchdog timer, the watchdog timer count source
selection bit (bit 7 of watchdog timer control register (address
3916)) before executing the STP instruction.
3. The STP instruction function selection bit (bit 6 of watchdog
timer control register (address 3916)) can be rewritten only once
after releasing reset. After rewriting it is disable to write any data
to this bit.