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Rev.2.00
Aug 28, 2006
page 4 of 13
7641 Group
REJ09B0336-0200
List of figures
CHAPTER 1 HARDWARE
Fig. 1 M37641M8-XXXFP, M37641F8FP pin configuration ......................................................... 3
Fig. 2 M37641M8-XXXHP, M37641F8HP pin configuration ........................................................ 3
Fig. 3 Functional block diagram ...................................................................................................... 4
Fig. 4 Part numbering ....................................................................................................................... 7
Fig. 5 Memory expansion plan ........................................................................................................ 8
Fig. 6 7600 series CPU register structure .................................................................................... 9
Fig. 7 Register push and pop at interrupt generation and subroutine call ............................ 10
Fig. 8 Structure of CPU mode register ........................................................................................ 12
Fig. 9 Memory map diagram ......................................................................................................... 13
Fig. 10 Memory map of special function register (SFR) ........................................................... 14
Fig. 11 Structure of port control and port P2 pull-up control registers ................................... 15
Fig. 12 Port block diagram (1) ...................................................................................................... 17
Fig. 13 Port block diagram (2) ...................................................................................................... 18
Fig. 14 Port block diagram (3) ...................................................................................................... 19
Fig. 15 Port block diagram (4) ...................................................................................................... 20
Fig. 16 Interrupt control ................................................................................................................ 21
Fig. 17 Structure of interrupt-related registers ............................................................................ 23
Fig. 18 Connection example when using key input interrupt and port P2 block diagram ... 24
Fig. 19 Timer block diagramn ....................................................................................................... 25
Fig. 20 Structure of timer X mode register ................................................................................. 26
Fig. 21 Structure of timer Y mode register ................................................................................. 27
Fig. 22 Structure of timer 123 mode register ............................................................................. 28
Fig. 23 Structure of serial I/O control registers 1, 2 ................................................................. 29
Fig. 24 Block diagram of serial I/O .............................................................................................. 30
Fig. 25 Serial I/O timing ................................................................................................................. 31
Fig. 26 UARTx (x = 1, 2) block diagram .................................................................................... 33
Fig. 27 UARTx transmit timing (CTS function enabled) ............................................................ 34
Fig. 28 UARTx transmit timing (CTS function disbled) ............................................................. 35
Fig. 29 UARTx transmit timing (RTS function enabled) .......................................................... 35
Fig. 30 Structure of UART related registers ............................................................................... 38
Fig. 31 DMACx (x = 0, 1) block diagram .................................................................................... 39
Fig. 32 Structure of DMACx related register ............................................................................. 40
Fig. 33 Timing chart for cycle steal transfer caused by hardware-related transfer request
............................................................................................................................................ 42
Fig. 34 Timing chart for cycle steal transfer caused by software trigger transfer request .. 42
Fig. 35 Timing chart for burst transfer caused by hardware-related transfer request .......... 43
Fig. 36 USB FCU (USB Function Control Unit) block ............................................................... 44
Fig. 37 Structure of USB control register .................................................................................... 48
Fig. 38 Structure of USB address register .................................................................................. 49
Fig. 39 Structure of USB power management register ............................................................. 49
Fig. 40 Structure of USB interrupt status register 1 ................................................................ 50
Fig. 41 Structure of USB interrupt status register 2 ................................................................ 51
Fig. 42 Structure of USB interrupt enable register 1 ............................................................... 52
Fig. 43 Structure of USB interrupt enable register 2 ............................................................... 52
Fig. 44 Structure of USB frame number registers ..................................................................... 53
List of figures