36
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 46 Watchdog timer block diagram
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software run-away.
Figure 46 shows a block diagram of the watchdog timer. The
watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts the clock frequency divided by 32 (f
32
)
or by 512 (f
512
). Whether to count f
32
or f
512
is determined by the
watchdog timer frequency selection flag shown in Figure 47. f
512
is selected when the flag is “0” and f
32
is selected when it is “1”.
The flag is cleared after reset. FFF
when “L” or 2V
CC
is applied to the RESET pin, STP instruction is
executed, data is written to the watchdog timer, or the most signifi-
cant bit of the watchdog timer become “0”.
After FFF
16
is set in the watchdog timer, the contents of watchdog
timer is decremented by one at every cycle of selected frequency
f
32
or f
512
, and after 2048 counts, the most significant bit of watch-
dog timer become “0”, and a watchdog timer interrupt request bit
is set, and FFF
16
is preset in the watchdog timer.
Normally, a program is written so that data is written in the watch-
dog timer before the most significant bit of the watchdog timer
become “0”. If this routine is not executed due to unexpected pro-
gram execution, the most significant bit of the watchdog timer
become eventually “0” and an interrupt is generated.
The processor can be reset by setting the bit 3 (software reset bit)
of processor mode register described in Figure 10 in the interrupt
section and generating a reset pulse.
The watchdog timer stops its function when the RESET pin volt-
age is raised to double the V
CC
voltage.
The watchdog timer can also be used to recover from when the
clock is stopped by the STP instruction. Refer to the section on
clock generation circuit for more details.
The watchdog timer hold the contents during a hold state and the
frequency is stopped to input.
Fig. 47 Watchdog timer frequency selection flag
Watchdog timer
frequency selection (connection forced to f
32
during
STP instruction execution)
Set “FFF
16
”
Write to watchdog
timer
d2Vcc
circuit
S
Q
R
RESET
STP instruction
f
512
f
32
Watchdog timer
(60
16
)
Hold
0 : Select f
512
1 : Select f
32
7
61
16
Address
Watchdog timer
frequency selection
6
5
4
3
2
1
0