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| 型號(hào)： | M37754S4CHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 0.50 MM PITCH, FINE PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 25/114頁(yè) |
| 文件大小： | 1116K |
| 代理商： | M37754S4CHP |
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
18
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 2 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and is
discussed in this section, too.
___
DBC is an interrupt used during debugging.
___
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 3 shows the
addresses of the interrupt control registers and Figure 10 shows the
bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
___
bits other than DBC and watchdog timer can be cleared by software.
____
___
INT4 to INT0 are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
___
__
In the INT3 external interrupt, the INT3 input, KI3 to KI0 inputs, or KI4
__
____
to KI0 inputs can be selected with bits 7 and 6 of INT3 interrupt con-
trol register.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused simul-
taneously is partially fixed by hardware, but, it can also be adjusted
by software as shown in Figure 11.
The hardware priority is fixed as the following:
___
reset > DBC > watchdog timer > other interrupts
Table 2. Interrupt types and the interrupt vector addresses
Interrupts
____
INT4 external interrupt
____
INT3 external interrupt
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
____
INT2 external interrupt
____
INT1 external interrupt
____
INT0 external interrupt
Watchdog timer
____
DBC (Do not select.)
Break instruction
Zero divide
Reset
Vector addresses
00FFD216
00FFD316
00FFD416
00FFD516
00FFD616
00FFD716
00FFD816
00FFD916
00FFDA16
00FFDB16
00FFDC16
00FFDD16
00FFDE16
00FFDF16
00FFE016
00FFE116
00FFE216
00FFE316
00FFE416
00FFE516
00FFE616
00FFE716
00FFE816
00FFE916
00FFEA16
00FFEB16
00FFEC16
00FFED16
00FFEE16
00FFEF16
00FFF016
00FFF116
00FFF216
00FFF316
00FFF416
00FFF516
00FFF616
00FFF716
00FFF816
00FFF916
00FFFA16
00FFFB16
00FFFC16
00FFFD16
00FFFE16
00FFFF16
Fig. 10 Interrupt control register bit configuration
76543210
Interrupt priority level
Interrupt request bit (Note 1)
0 : No interrupt
1 : Interrupt
76543210
Interrupt priority level
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity select bit
0 : Set interrupt request bit at “H” level for level sense and when changing from “H” to “L”
level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing from “L” to “H”
level for edge sense.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Key input interrupt select bits 1, 0 (only for INT3 interrupt control register)
0 0 : INT3 interrupt selected
0 1 : Do not select.
1 0 : Key input interrupt (KI3 to KI0) selected
1 1 : Key input interrupt (KI4 to KI0) selected
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2.
Note 1: The A-D conversion interrupt request bit becomes undefined after reset. Clear this bit to “0” before use of the A-D conversion interrupt.
Interrupt control register configuration for INT4– INT0 (Note 2).
Note 2: The contents of INT4 interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see
Figure 15) is set to “1.”
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