參數(shù)資料
型號： M38005S8-XXXHP
廠商： Mitsubishi Electric Corporation
元件分類： 串行ADC
英文描述： 8-Bit 41 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 4 Ch. 14-SOIC
中文描述： 8位單片機
文件頁數(shù)： 12/173頁
文件大小： 4203K
代理商： M38005S8-XXXHP
iv
3800 GROUP USER’S MANUAL
List of figures
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics......................................... 3-11
Fig. 3.1.2 Timing diagram (in single-chip mode) .................................................................... 3-12
Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1) 3-13
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2) 3-14
Fig. 3.2.1 Power source current characteristic example ....................................................... 3-15
Fig. 3.2.2 Power source current characteristic example (in wait mode)............................. 3-15
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1). 3-16
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2). 3-16
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) 3-17
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) 3-17
Fig. 3.3.1 Structure of interrupt control register 2.................................................................. 3-18
Fig. 3.4.1 Wiring for the RESET pin ........................................................................................ 3-24
Fig. 3.4.2 Wiring for clock I/O pins........................................................................................... 3-25
Fig. 3.4.3 Wiring for the V
PP
pin of the One Time PROM and the EPROM version....... 3-25
Fig. 3.4.4 Bypass capacitor across the V
SS
line and the V
CC
line..................................... 3-25
Fig. 3.4.5 Wiring for a large current signal line ..................................................................... 3-26
Fig. 3.4.6 Wiring to a signal line where potential levels change frequently ...................... 3-26
Fig. 3.4.7 Stepup for I/O ports .................................................................................................. 3-26
Fig. 3.4.8 Watchdog timer by software .................................................................................... 3-27
Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7)........................................................ 3-28
Fig. 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7)......................... 3-28
Fig. 3.5.3 Structure of Transmit/Receive buffer register ....................................................... 3-29
Fig. 3.5.4 Structure of Serial I/O status register .................................................................... 3-29
Fig. 3.5.5 Structure of Serial I/O control register................................................................... 3-30
Fig. 3.5.6 Structure of UART control register ......................................................................... 3-30
Fig. 3.5.7 Structure of Baud rate generator ............................................................................ 3-31
Fig. 3.5.8 Structure of Prescaler 12, Prescaler X, Prescaler Y ........................................... 3-31
Fig. 3.5.9 Structure of Timer 1.................................................................................................. 3-32
Fig. 3.5.10 Structure of Timer 2, Timer X, Timer Y .............................................................. 3-32
Fig. 3.5.11 Structure of Timer XY mode register ................................................................... 3-33
Fig. 3.5.12 Structure of Interrupt edge selection register ..................................................... 3-34
Fig. 3.5.13 Structure of CPU mode register............................................................................ 3-34
Fig. 3.5.14 Structure of Interrupt request register 1 .............................................................. 3-35
Fig. 3.5.15 Structure of Interrupt request register 2 .............................................................. 3-35
Fig. 3.5.16 Structure of Interrupt control register 1 ............................................................... 3-36
Fig. 3.5.17 Structure of Interrupt control register 2 ............................................................... 3-36
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