參數(shù)資料
型號： M38005S8-XXXHP
廠商： Mitsubishi Electric Corporation
元件分類： 串行ADC
英文描述： 8-Bit 41 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 4 Ch. 14-SOIC
中文描述： 8位單片機
文件頁數(shù)： 34/173頁
文件大?。?/td> 4203K
代理商： M38005S8-XXXHP
1-20
HARDWARE
3800 GROUP USER’S MANUAL
Timers
The 3800 group has four timers: timer X, timer Y, timer 1, and timer
2.
All timers are count down. When the timer reaches “00
16
”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency di-
vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each be selected in one of four operating
modes by setting the timer XY mode register.
Timer Mode
The timer counts f(X
IN
)/16 in timer mode.
Pulse Output Mode
Timer X (or timer Y) counts f(X
IN
)/16. Whenever the contents of
the timer reach “00
16
”, the signal output from the CNTR
0
(or
CNTR
1
) pin is inverted. If the CNTR
0
(or CNTR
1
) active edge
switch bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P5
4
( or port P5
5
) direction register to out-
put mode.
Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except the timer counts signals input through the CNTR
0
or
CNTR
1
pin.
Pulse Width Measurement Mode
If the CNTR
0
(or CNTR
1
) active edge selection bit is “0”, the timer
counts at the oscillation frequency divided by 16 while the CNTR
0
(or CNTR
1
) pin is at “H”. If the CNTR
0
(or CNTR
1
) active edge
switch bit is “1”, the count continues during the time that the
CNTR
0
(or CNTR
1
) pin is at “L”.
In all of these modes, the count can be stopped by setting the
timer X (timer Y) count stop bit to “1”. Every time a timer
underflows, the corresponding interrupt request bit is set.
Fig. 15 Structure of timer XY register
FUNCTIONAL DESCRIPTION
Timer X count stop bit
0: Count start
1: Count stop
Timer XY mode register
(TM : address 0023
16)
Timer Y operating mode bit
0
0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR
active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
b7
CNTR
0
active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
b0
Timer X operating mode bit
b1b0
0
0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
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