參數(shù)資料
型號： M38005S8-XXXSS
廠商： Mitsubishi Electric Corporation
元件分類： 串行ADC
英文描述： 8-Bit 41 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 4 Ch. 14-SOIC
中文描述： 8位單片機(jī)
文件頁數(shù)： 167/173頁
文件大小： 4203K
代理商： M38005S8-XXXSS
3800 GROUP USER’S MANUAL
APPENDIX
3.9 Machine instructions
Addressing mode
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
7 6 5 4 3 2 1 0
Processor status register
N
V
T
B
D
I
Z
C
OP n
# OP n
# OP
n
# OP
n
# OP
n
# OP n
# OP n
#
OP n
#
OP n
#
OP
n
# OP n
#
3-65
95
94
N
N
N
N
N
N
Z
Z
Z
Z
Z
Z
Addition
Subtraction
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Memory specified by address designation of any ad-
dressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by AD
H
and
AD
L
, in AD
H
is 8 high-order bits and AD
L
is 8 low-or-
der bits.
Contents of address indicated by zero page AD
L
1 bit of accumulator
1 bit of memory
Opcode
Number of cycles
Number of bytes
5
5
2
2
96 5
2
8D
8E
8C
5
5
5
3
3
3
9D 6
3 99 6
3
81 7
2 91 7
2
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
Zero page indirect absolute addressing mode
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
IMP
IMM
A
BIT, A
ZP
BIT, ZP
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Symbol
Contents
Symbol
Contents
+
–
V
V
V
–
←
X
Y
S
PC
PS
PC
H
PC
L
AD
H
AD
L
FF
nn
M
M(X)
M(S)
M(AD
H
, AD
L
)
M(00, AD
L
)
Ab
Mb
OP
n
#
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