參數(shù)資料
型號： M38005S8-XXXSS
廠商： Mitsubishi Electric Corporation
元件分類： 串行ADC
英文描述： 8-Bit 41 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 4 Ch. 14-SOIC
中文描述： 8位單片機
文件頁數(shù)： 33/173頁
文件大?。?/td> 4203K
代理商： M38005S8-XXXSS
HARDWARE
1-19
3800 GROUP USER’S MANUAL
Fig. 13 Interrupt control
Fig. 14 Structure of interrupt-related registers
FUNCTIONAL DESCRIPTION
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
active edge selection bit
INT
1
active edge selection bit
INT
2
active edge selection bit
INT
3
active edge selection bit
INT
4
active edge selection bit
INT
5
active edge selection bit
Not used (return “0” when read)
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
interrupt request bit
INT
1
interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Interrupt request register 2
(IREQ2 : address 003D
16
)
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
INT
4
interrupt request bit
INT
5
interrupt request bit
Not used (return “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 2
(ICON2 : address 003F
16
)
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
INT
2
interrupt enable bit
INT
3
interrupt enable bit
INT
4
interrupt enable bit
INT
5
interrupt enable bit
Not used (return “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Falling edge active
1 : Rising edge active
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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