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參數(shù)資料
| 型號： | M38027M4D1024FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Advanced LinCMOS(TM) Rail-To-Rail Dual Operational Amplifier 8-SOIC -40 to 125 |
| 中文描述： | 8位單片機 |
| 文件頁數(shù)： | 151/207頁 |
| 文件大小： | 2389K |
| 代理商： | M38027M4D1024FP |
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3802 GROUP USER’S MANUAL
3-25
APPENDIX
3.3 Notes on use
Make sure the following :
G
Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
G
Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction,
its value may be changed in case where content of the pin differs from a content of the port latch.
* bit managing instructions :
SEB
and
CLB
instruction
(3) The AV
SS
pin when not using the A-D converter
When not using the A-D converter, handle a power source pin for the A-D converter, AV
SS
pin as follows :
G
AV
SS
: Connect to the V
SS
pin
G
G
G
G
Reason
If the AV
SS
pin is opened, the microcomputer may malfunction by effect of noise or others.
3.3.6 Notes on memory expansion mode and microprocessor mode
(1) Writing data to the port latch of port P3
In the memory expansion or the microprocessor mode, ports P3
0
and P3
1
can be used as the output port. Use the
LDM
or
STA
instruction for writing data to the port latch (address 0006
16
) of port P3.
When using a read-modify-write instruction (the
SEB
or the
CLB
instruction), allocate the read and the write
enabled memory at address 0006
16
.
Reason
In the memory expansion or microprocessor mode, address 0006
16
is allocated in the external area.
Accordingly,
Data is read from the external memory.
Data is written to both the port latch of the port P3 and the external memory.
Accordingly, when executing a read-modify-write instruction for address 0006
16
, external memory data is read and
modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled
memory is not allocated at address 0006
16
, the read data is undefined. The undefined data is modified and written
to the port latch of the port P3. The port latch data of port P3 becomes “undefined.”
(2) Overlap of an internal memory and an external memory
When the internal and the external memory are overlapped in the memory expansion mode, the internal memory
is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed :
When reading data
Only the data in the internal memory is read into the CPU and the data in the external memory is not read into
the CPU. However, as the read signal and address are still valid, the external memory data of the
corresponding address is output to the external data bus.
When writing data
Data is written in both the internal and the external memory.
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