參數(shù)資料
型號(hào)： M38073E4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 2/74頁(yè)
文件大?。?/td> 1182K
代理商： M38073E4-XXXFP
10
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction Registers] PiD
The 3807 group has 68 programmable I/O pins arranged in nine indi-
vidual I/O ports (P0—P5, P60—P62, P65 and P7—P8). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, each pin can be set to be input port or output port. When "0"
is written to the bit corresponding to a pin, that pin becomes an input
pin. When "1" is written to that pin, that pin becomes an output pin. If
data is read from a pin set to output, the value of the port output latch
is read, not the value of the pin itself. Pins set to input (the bit corre-
sponding to that pin must be set to "0") are floating and the value of
that pin can be written to. If a pin set to input is written to, only the
port output latch is written to and the pin remains floating.
[Pull-up Control Register] PULL
Ports P0, P1 and P2 have built-in programmable pull-up resistors.
The pull-up resistors are valid only in the case that the each control
bit is set to "1" and the corresponding port direction registers are set
to input mode.
(1) CMOS/TTL input level selection
Either CMOS input level or TTL input level can be selected as an
input level for ports P20 to P27 and P32. The input level is selected by
P2P32 input level selection bit (b7) of the port P2P3 control register
(address 001516). When the bit is set to "0", CMOS input level is
selected. When the bit is set to "1", the TTL input level is selected.
After this bit is re-set, its initial value depends on the state of the
CNVss pin. When the CNVss pin is connected to Vss, the initial value
becomes "0". When the CNVss pin is connected to Vcc, the initial
value becomes "1".
(2) Notes on STP instruction execution
Make sure that the input level at each pin is either 0V or to Vcc during
execution of the STP instruction. When an input level is at an inter-
mediate potential, a current will flow from Vcc to Vss through the
input-stage gate.
Fig. 8. Structure of Port P2P3 control register
Fig. 9. Structure of Pull-up control register
b7
Port P2P3 control register
(P2P3C : address 001516)
P34 Clock output control bit
0: I/O port
1: Clock output
Output clock frequency selection bit
000:
φ
001: f(XCIN)
010: “L” fixed output
011: “L” fixed output
100: f(XIN)
(f(XCIN) in low-speed mode)
101: f(XIN)/2
(f(XCIN)/2 in low-speed mode)
110: f(XIN)/4
(f(XCIN)/4 in low-speed mode)
111: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
Not used (return "0" when read)
P2 P32 input level selection bit
0: CMOS level input
1: TTL level input
b0
0: No pull-up
1: Pull-up
Pull-up control register
(PULL : address 001616)
P00—P03 pull-up control bit
P04,P05 pull-up control bit
P06 pull-up control bit
P07 pull-up control bit
P10—P13 pull-up control bit
P14—P17 pull-up control bit
P20—P23 pull-up control bit
P24—P27 pull-up control bit
b7
b0
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