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參數(shù)資料
| 型號(hào)： | M38073E4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 22/74頁 |
| 文件大小： | 1182K |
| 代理商： | M38073E4-XXXFP |
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29
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
qTimer 1, Timer 2, Timer 3
Timer 1 to 3 are 8-bit timers for which the count source can be se-
lected through timer 123 mode register.
(1) Timer 2 write control
Timer 2 write control bit (b2) of timer 123 mode register allows to
select whether a value written to timer 2 is written to timer latch and
timer synchronously or to the timer latch only.
If only the timer latch is written to, the value is set only to the reload-
latch by writing a value to the timer address at that time. The
content of timer is reloaded with the next underflow. Usually writing
operation to the timer latch and timer synchronously is selected. And
a value is written to the timer latch and timer synchronously when a
value is written to the timer address.
If only the timer latch is written to, it may occur that the value set to
the counter is not constant, when the timing with which the reload-
latch is written to and the underflow timing is nearly the same.
(2) Timer 2 output control
When timer 2 output (TOUT) is enabled, inverted signals are output
from TOUT pin each time timer 2 has underflow. For this reason, set
the double-function port of TOUT pin to output mode.
sPrecautions on timers 1 to 3
When the count source for timer 1 to 3 is switched, it may occur that
short pulses are generated in count signals and that the timer count
value shows big changes. When timer 1 output is selected as timer 2
or timer 3 count source, short pulses are generated to
signals output from timer 1 through writing timer 1. Due to that, the
count values for timer 2 and 3 may change very often.
Therefore, when the count sources for timer 1 to 3 are set, set the
values in order starting from timer 1.
Fig. 25. Block diagram of Timer
Fig. 24. Structure of Timer 123 mode register
Timer 1 count source
selection bits
Timer 3 latch (8)
Timer 3 (8)
Q
T
S
"00"
P50 direction
register
P50 latch
"0"
"1"
TOUT output active
edge switch bit
Timer 2 write
control bit
"0"
"1"
"10"
P50/TOUT
Timer 3 count source
selection bit
"0"
"1"
Timer 2
interrupt
request
Timer 3
interrupt
request
TOUT output control bit
Timer 2 count source
selection bit
Timer 1 latch (8)
Timer 1 (8)
Timer 1
interrupt
request
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
"01"
Data bus
f(XCIN)
f(XIN)/2
(f(XCIN)/2 in low-speed mode)
Timer 2 latch (8)
Timer 2 (8)
TOUT output
control bit
TOUT output active edge switch bit
0 : start with "H" output
1 : start with "L" output
Timer 123 mode register
(T123M : address 002916)
b7
b0
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode)
Not used (returns “0” when read)
Timer 1 count source selection bits
00 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode)
01 : f(XIN)/2 (or f(XCIN)/2 in low-speed mode)
10 : f(XCIN)
11 : Not available
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode)
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