參數(shù)資料
型號： M38197MA-XXXKP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 13/63頁
文件大?。?/td> 870K
代理商： M38197MA-XXXKP
17
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
b7
Interrupt edge selection register
(INTEDGE : address 003A 16)
INT0 interrupt edge selection bit
INT1/ZCR interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
INT4 interrupt edge selection bit
INT4/AD conversion interrupt switch bit
CNTR0 pin active edge switch bit
CNTR1 pin active edge switch bit
b0
0 : Falling edge active
1 : Rising edge active
0 : No interrupt request issued
1 : Interrupt request issued
0 : INT4 interrupt
1 : A-D conversion interrupt
0 : Rising edge count
1 : Falling edge count
b7
Interrupt request register 1
(IREQ1 : address 003C16)
INT0 interrupt request bit
INT1/ZCR interrupt request bit
INT2 interrupt request bit
Remote control/counter overflow
interrupt request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer
interrupt request bit
Serial I/O2 interrupt request bit
Serial I/O3 interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
b0
b7
Interrupt request register 2
(IREQ2 : address 003D16)
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
b0
0 : Interrupts disabled
1 : Interrupts enabled
b7
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1/ZCR interrupt enable bit
INT2 interrupt enable bit
Remote control/counter overflow
interrupt enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer
interrupt enable bit
Serial I/O2 interrupt enable bit
Serial I/O3 interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
b0
b7
Interrupt control register 2
(ICON2 : address 003F 16)
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(do not write “1” to this bit)
b0
Fig. DD-1 Interrupt control
Fig. DD-2 Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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