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參數(shù)資料
| 型號(hào)： | M38197MA-XXXKP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 26/63頁 |
| 文件大小： | 870K |
| 代理商： | M38197MA-XXXKP |
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29
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table GA-2. P67/SRDY1/CS selection
(2.4) When Selecting the External Clock
When selecting the external clock, the internal clock and the set-
ting of transfer interval with the serial I/O automatic transfer
interval register are invalid, but the serial I/O output pin SOUT1 and
the internal transfer clock can be controlled from the outside by
setting the SRDY1 pin to the CS (input) pin.
When the CS input is “L”, the SOUT1 pin and the internal transfer
clock are enabled.
When the CS input is “H”, the SOUT1 pin goes to high impedance
state and the internal transfer clock goes to “H”.
Select the function of the P67/SRDY1/CS/SCLK12 with the following
registers (refer to Table GA-2):
qthe bit 4 (SC14) and the bit 6 (SC16) of the serial I/O1 control
register
qthe bit 0 (SIOAC0) of the serial I/O automatic transfer control
register
Switch the CS pin from “L” to “H” or from “H” to “L” during “H” of the
transfer clock (SCLK11 input) after transferring 1-byte data.
When selecting the external clock, set the external clock to “L” af-
ter 9 cycles or more of the internal clock
φ after setting the start
bit. After transferring 1-byte data, leave 11 cycles or more of the
internal clock
φ free for the transfer interval.
When not using the CS input, note that the SOUT pin will not go to
high impedance state, even after transfer is completed.
When not using the CS input, or when CS is “L”, control the exter-
nal clock because the data in the serial I/O register will continue to
shift while the external clock is input, even after the completion of
automatic transfer (Note that the automatic transfer interrupt re-
quest bit is set and the bit 1 of the serial I/O automatic transfer
register is cleared at the point when the specified number of bytes
of data have been transferred.)
SC16
0
SC14
0
1
SIOAC0
!
0
1
P67/SRDY1/CS
P67
SRDY1
CS
Note : SC14: SRDY1 output selection bit
SC16: Synchronous clock selection bit
SIOAC0: Automatic transfer control bit
Fig. GA-10 Timing during serial I/O automatic transfer (external clock selected)
X
Bit 1 write signal of serial I/O
automatic transfer control
register
Serial I/O output
SOUT
Serial I/O input
SIN
Note: Data marked with X is invalid.
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM
Transfer clock
(internal)
Data pointer
CS
n-1
n
DO0
X
Transfer clock
SCLK input
External input
X
DO1 DO2 DO3 DO4 DO5 DO6 DO7
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
X
XX
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