參數(shù)資料
型號： M38199MF-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 6/63頁
文件大小： 870K
代理商： M38199MF-XXXFP
11
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P62/CNTR0,
P63/CNTR1
P64/SIN1
P65/SOUT1,
P66/SCLK11
P67/SRDY1/
CS/SCLK12
Port P5
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
Diagram
No.
P50/SIN2/
AN8
P51/SOUT2/
AN9,
P52/SCLK2/
AN10
P53/SRDY2/
AN11
P54/SIN3/
AN12
P55/SOUT3/
AN13,
P56/SCLK3/
AN14
P57/SRDY3/
AN15
P60
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual bits
Serial I/O2 func-
tion I/O
A-D conversion in-
put
Serial I/O2 control
register
AD/DA control regis-
ter
(9)
Serial I/O3 func-
tion I/O
A-D conversion in-
put
Serial I/O3 control
register
AD/DA control regis-
ter
Timer 56 mode regis-
ter
PWM (timer) out-
put
P61/PWM
Timer input
Interrupt edge selec-
tion register
Serial I/O1 func-
tion I/O
Serial I/O1 control
register
Serial I/O automatic
transfer control regis-
ter
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
CMOS compatible
input level
High-breakdown-
voltage P-channel
open-drain output
P70/AN0–
P77/AN7
P80/SEG8–
P87/SEG15
P90/SEG16–
P97/SEG23
PA0/SEG0–
PA7/SEG7
PB0/XCOUT,
PB1/XCIN
PB2/DA
PB3
CMOS compatible
input level
CMOS 3-state output
FLD automatic
display function
A-D conversion in-
put
I/O for sub-clock
generating circuit
D-A conversion
output
AD/DA control regis-
ter
FLDC mode register
Segment/port switch
register
FLDC mode register
Segment/port switch
register
CPU mode register
AD/DA control regis-
ter
Output
Input/output,
individual bits
Input/output,
individual bits
Port P6
Port P7
Port P8
Port P9
Port PA
(10)
(11)
(9)
(10)
(11)
(4)
(8)
(7)
(9)
(10)
(11)
(12)
(13)
(5)
(13)
(14)
(15)
(16)
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-
tial, a current will flow from VCC to VSS through the input-stage gate.
Port PB
CMOS compatible
input level
CMOS 3-state output
(4)
相關(guān)PDF資料
PDF描述
M38199EF-XXXFP 8-BIT, OTPROM, 4.2 MHz, MICROCONTROLLER, PQFP100
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M38197MA-XXXFP 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
M38197MA-XXXKP 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
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