Page
Corrections and Supplementary Explanation for “3822 Group User’s Manuals” No.1
P1-20
(Left columun)
P1-22
line 7
(Right column)
P2-40
line 8
P2-65
(1) Timer X
s Timer mode
Fig. 2.3.22
P2-66
(1) Timer X
s Pulse output mode
Fig. 2.3.23
Error
A key input interrupt request is generated by applying “L” level ...
Correct
A key input interrupt request is generated by detecting falling edge..
Error
(However, if the real time port control bit is changed from “0” to “1”,
data are output without the timer X.)
Correct
(However, after rewriting a data storage bit for real time port, if the
real time port control bit is changed from “0” to “1”, data is output
without the timer X.)
Error
A data output from the real time port is started at setting the real
time port control bit to “1”.
Correct
A data output from the real time port is started at setting the real
time port control bit to “1” (when setting “1” to the real time port
control bit of the timer X mode register, use the SEB instruction).
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the timer X interrupt enable
bit and the timer X interrupt request bit to “0”.
After setting below, set the timer X interrupt enable bit
to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer X stops counting (before setting below),
clear the timer X interrupt enable bit to “0”.
After setting below, clear the timer X interrupt request
bit to “0” and next set the timer X interrupt enable bit to
“1” (interrupt enabled).
Set last.
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the interrupt enable bits
(timer X or CNTR0) and the interrupt request bits (timer
X or CNTR0) to “0”.
After setting below, set the interrupt enable bits (timer
X or CNTR0) to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer X stops counting (before setting below),
clear the interrupt enable bit (timer X or CNTR0) to “0”.
After setting below, clear the interrupt request bit (timer
X or CNTR0) to “0” and next set the interrupt enable bit
(timer X or CNTR0) to “1” (interrupt enabled).
Set last.
M380-17-9910
(2/5)
Rev.
Contents
C
A
B