2.1 I/O pins
APPLICATION
3822 GROUP USER’S MANUAL
2–3
Table 2.1.1 shows the memory allocation of
the port registers corresponding to each port.
Table 2.1.1 Memory allocation of port registers
Port
Port register address
000016
000216
000416
000616
000816
000A16
000C16
000E16
P2
P3
P4
P5
P6
P7
P0
P1
(2) Input/output switching of programmable I/O ports
Input/output switching of the programmable I/O ports is performed by the port direction register cor-
responding to each port (Note). Figure 2.1.2 shows the structure of the port Pi (i = 2, 4 to 7) direction
register, and Table 2.1.2 shows the memory allocation of the port direction registers corresponding to
each port. Figure 2.1.4 shows a port direction register setting example.
Note: In ports P0 and P1, input/output switching is performed by a port unit. By setting bit 0 of the
corresponding direction register to “0,” the port is set for the input mode. By setting to “1,” the
port is set for the output mode. Figure 2.1.3 shows the structure of the ports P0 and P1
direction registers.
Fig. 2.1.2 Structure of port Pi (i = 2, 4 to 7) direction register
Notes 1: Nothing is allocated bit 0 of port P4 direction register and bit 2
to bit 7 of port P7 direction register. These bits cannot be written
to.
2: The contents of the port Pi direction register cannot be read out
(refer to “2.1.4 Notes on use” )
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 2, 4 to 7)
[Address 0516, 0916, 0B16, 0D16, 0F16]
B
Name
Functions
At reset
R
W
Port Pi direction register
0
1
2
3
4
5
6
7
Port Pi direction
register
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
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