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參數(shù)資料
| 型號： | M38257E8GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 35/73頁 |
| 文件大?。?/td> | 1323K |
| 代理商： | M38257E8GP |
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Rev.2.02
Jun 19, 2007
page 38 of 73
REJ03B0146-0202
3823 Group
A/D CONVERTER
[AD Conversion Register (ADH, ADL)] 003516
The AD conversion register is a read-only register that contains
the result of an A/D conversion. When reading this register during
an A/D conversion, the previous conversion result is read.The
high-order 8 bits of a conversion result is stored in the AD conver-
sion high-order register (address 003516),and the low-order 2 bits
of the same result are stored in bit 7 and bit 6 of the AD conver-
sion low-order register (address 003616).
The bit 0 in the AD conversion low-order register is used as the
conversion mode selection bit. 8-bit A/D mode is selected by set-
ting this bit to “0” and 10-bit A/D mode is selected by setting it to
“1”.
[AD Control Register (ADCON)] 003416
The AD control register controls the A/D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A/D conversion. The value of this bit remains
at “0” during an A/D conversion, then changes to “1” when the
A/D conversion is completed. Writing “0” to this bit starts the A/D
conversion. Bit 4 is the VREF input switch bit which controls con-
nection of the resistor ladder and the reference voltage input pin
(VREF). The resistor ladder is always connected to VREF when bit
4 is set to "1". When bit 4 is set to “0”, the resistor ladder is cut off
from VREF except for A/D conversion performed. When bit 5,
which is the AD external trigger valid bit, is set to “1”, this bit en-
ables A/D conversion even by a falling edge of an ADT input. Set
the P57/ADT pin to input mode (set "0" to bit 7 of port P5 direction
register) when using an A/D external trigger.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the AD
conversion register. When an A/D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The conver-
sion accuracy may be low because the charge is lost if the
conversion speed is not enough. Accordingly, set f(XIN) to at least
500kHz during A/D conversion in the middle-or high-speed mode.
Also, do not execute the STP or WIT instruction during an A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by
the built-in self-oscillation circuit, the minimum value of f(XIN) fre-
quency is not limited.
Fig. 33 Structure of AD conversion-related registers
AD control register
(ADCON : address 003416)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
VREF input switch bit
0 : ON during conversion
1 : Always ON
AD external trigger valid bit
0 : A/D external trigger invalid
1 : A/D external trigger valid
b7
b0
Interrupt source selection bit
0 : Interrupt request at A/D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
AD conversion low-order register
(ADL : address 003616)
AD conversion speed selection bit
00 : f(XIN)/2
(this can be used in CPUM7 = “0” )
01 : f(XIN)
(this can be used in CPUM7 = “0” )
10 : On-chip oscillator
(this can be used in CPUM7 = “0”
and EXPCM0 = “1”)
11 : Disabled
Conversion mode selection bit
0 : 8 bit A/D mode
1 : 10 bit A/D mode
Not used (returns “0” when read)
In 10-bit A/D mode
A/D conversion data storage
In 8-bit A/D mode
Not used (Indefinite at read)
b7
b0
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